Microcode
Intel-Linux-Processor-Microcode-Data-Files | Microcode | |
---|---|---|
20 | 4 | |
651 | 324 | |
1.8% | - | |
4.6 | 0.0 | |
about 1 month ago | almost 6 years ago | |
Python | ||
GNU General Public License v3.0 or later | - |
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Intel-Linux-Processor-Microcode-Data-Files
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There is no fix for Intel's crashing 13th/14th Gen CPUs – damage is permanent
So where is the microcode update? I don't see anything for Linux yet.
https://github.com/intel/Intel-Linux-Processor-Microcode-Dat...
- Intel Issues New CPU Microcode Going Back To Gen8 For New, Undisclosed Security Updates
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N100 wait or done with it ?
https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/blob/main/releasenote.md looks like they released a new microcode (24000024) affecting these units on Feb 14th this year.
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Why is intel-microcode missing in the unstable repo?
Package: intel-microcode Version: 3.20221108.1 Priority: optional Section: non-free/admin Maintainer: Henrique de Moraes Holschuh Installed-Size: 6460 kB Depends: iucode-tool (>= 1.0) Recommends: initramfs-tools (>= 0.113~) Conflicts: microcode.ctl (<< 0.18~0) Homepage: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files Tag: hardware::TODO, role::app-data, use::driver Download-Size: 4509 kB APT-Sources: http://deb.debian.org/debian testing/non-free amd64 Packages Description: Processor microcode firmware for Intel CPUs
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On “I don't trust microcode”
They have been sort of cracked, but it doesn't matter. The web or chain of trust of those updates from the vendor to the processor is what matters. They're at least CRC checked to prevent loading corrupt files.
https://ieeeaccess.ieee.org/featured-articles/reverseenginee...
https://github.com/intel/Intel-Linux-Processor-Microcode-Dat...
https://github.com/platomav/CPUMicrocodes
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Westworld - 4x06 "Fidelity" - Post-Episode Discussion
Not to “well aktchually”, but all modern processors do have regularly updated microcode that’s uploaded at boot time - https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files
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My CPU's microcode is missing
6-94-3 would become 6-5E-3. https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/blob/6c0c4691e5bb446e0e428ebca595164709c59586/intel-ucode/06-5e-03
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amd cpu firmware microcode ? (-current)
OpenBSD kernel has no support for loading microcode on AMD CPUs, A number of issues/errata on AMD systems may be fixed as part of AGESA updates, in addition to microcode as part of BIOS/firmware updates. While there have been microcode updates released for Zen+ or newer CPUs, but these seem to be less frequent than Intel.
- Will you still use Cloudready? Yes/No and why? Please...
- Why is it assumed that microcode updates improve security?
Microcode
- The legend of “x86 CPUs decode instructions into RISC form internally”
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On “I don't trust microcode”
For the Intel stuff you're talking about, there's three classes keys in play, two of which have been leaked, but not the one that allows you to impersonate Intel. What we have are the keys shipped on every actual system (that has been cracked, I think that's just for Goldmont), the symmetric encrypt/decrypt key (AES IIRC), and the public signing key to verify that it came from Intel. Intel's private keys behind the signature haven't been leaked.
Interestingly though, it turns out that AMD K10 microcode updates weren't signed and had only the laziest form of encryption, allowing some security researchers to make custom ucode updates using this toolchain they posted on github: https://github.com/RUB-SysSec/Microcode
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Simulating the IBM 360/50 mainframe from its microcode
From what little we know of recent designs (the best public documentation being the fantastic work to reverse engineer AMD K8 and K10 microcode here https://github.com/RUB-SysSec/Microcode ), I'd describe x86 microcode as particularly wide vertical microcode of 64 bit ops.
The bit width is more a heuristic. With horizontal microcode you can look at each group of bits and it's clear 'these three bits are the selection input to this mux', 'this bit is an enable for the buffer linking these two buses', etc. Vertical microcode in contrast is further decoded with bit fields having different meanings based on opcode style fields.
Pretty universally, OoO superscalar cores will use vertical microcode (or vertical microcode looking micro-ops in cores without microcode) because that's the right abstraction you want at the most expensive part of the design: the tracking of in flight and undispatched operations in the reorder buffer, and how the results route in the bypass network. Any additional wodtch there really starts to hit your power budget, and it's the wrong level for horizontal microcode because the execution units will make different choices on even how many control signals they want.
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Looking for a processor with no backdoors but has VT-x and VT-d (or equivalent). Thoughts?
any chip that you can't physically inspect might have backdoors. and if a CPU has updatable microcode, it's possible to implement a backdoor in microcode. there's no way to make a verifiably safe CPU with the features you want.
What are some alternatives?
nonguix - Nonguix mirror – pull requests ignored, please use upstream for that
uCodeDisasm
iota - A terminal-based text editor written in Rust
ghidra_a29k - Ghidra AMD 29000 (a29k) Processor Module
pacman-bintrans - Experimental pacman integration for Reproducible Builds and Binary Transparency (with sigstore/rekor)
CPUMicrocodes - Intel, AMD, VIA & Freescale CPU Microcode Repositories
score - ossia score, an interactive sequencer for the intermedia arts
Intel-Linux-Processor-Microcode-Dat
dysnomia - Dysnomia: A tool for deploying mutable components
userscan - Scans files for Nix store references and registers them with the Nix garbage collector.
nonguix
cargo-crev - A cryptographically verifiable code review system for the cargo (Rust) package manager.