CIC
Cascaded integrator-comb written in Chisel HDL (by Martoni)
chisel-formal
By tdb-alcorn
| CIC | chisel-formal | |
|---|---|---|
| 1 | 1 | |
| 2 | 21 | |
| - | - | |
| 2.6 | 0.0 | |
| 5 months ago | about 3 years ago | |
| C++ | Scala | |
| The Unlicense | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
CIC
Posts with mentions or reviews of CIC.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-09-15.
-
What is the canonical way to test and simulate Chisel gateware ?
Verilator (C++): I'm using Verilator with my own C++ classes to speed up simulation. This is the fastest solution by far for simulation time. But writing the testbench is not easy and It seems like we spend our time reinventing the wheel.
chisel-formal
Posts with mentions or reviews of chisel-formal.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-09-15.
-
What is the canonical way to test and simulate Chisel gateware ?
Formal (Yosys-smtbmc/chisel-formal): This is a really different approach to simulation with property checking. I first tryied it on generated verilog, then with chisel-formal module. This is a solution that is not yet mature for Chisel in my opinion.
What are some alternatives?
When comparing CIC and chisel-formal you can also consider the following projects:
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python