BYU_PYNQ_PR_Video_Pipeline_Hardware
BYU Pynq PR Video Pipeline Hardware (by byuccl)
gateware
IP submodules, formatted for easier CI integration (by betrusted-io)
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| BYU_PYNQ_PR_Video_Pipeline_Hardware | gateware | |
|---|---|---|
| 2 | 1 | |
| 7 | 25 | |
| - | - | |
| 0.0 | 5.7 | |
| over 4 years ago | 5 months ago | |
| VHDL | Verilog | |
| - | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
BYU_PYNQ_PR_Video_Pipeline_Hardware
Posts with mentions or reviews of BYU_PYNQ_PR_Video_Pipeline_Hardware.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-11-15.
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References for video system design on FPGAs.
Here is my example: Thesis: https://scholarsarchive.byu.edu/etd/8620/ HW: https://github.com/byuccl/BYU_PYNQ_PR_Video_Pipeline_Hardware SW: https://github.com/byuccl/BYU_PYNQ_PR_Video_Pipeline
- Share some github FPGA projects (bonus if they include C++, Python, or other files)
gateware
Posts with mentions or reviews of gateware.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-09-14.
-
Share some github FPGA projects (bonus if they include C++, Python, or other files)
A lot of reuse from other FOSH projects, including Litex, SpinalHDL, betrusted & u/alexforencich verilog-wishbone. Thanks to all of them :-)
What are some alternatives?
When comparing BYU_PYNQ_PR_Video_Pipeline_Hardware and gateware you can also consider the following projects:
verilog-ethernet - Verilog Ethernet components for FPGA implementation
SpinalHDL - Scala based HDL
litex - Build your hardware, easily!
WARP_Core - Wilson AXI RISCV Processor Core
satcat5 - SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
SBusFPGA - Stuff to put a FPGA in a SBus system (SPARCstation)
verilog-wishbone - Verilog wishbone components
BYU_PYNQ_PR_Video_Pipeline_Hardware vs verilog-ethernet
gateware vs verilog-ethernet
BYU_PYNQ_PR_Video_Pipeline_Hardware vs SpinalHDL
gateware vs litex
BYU_PYNQ_PR_Video_Pipeline_Hardware vs WARP_Core
gateware vs satcat5
BYU_PYNQ_PR_Video_Pipeline_Hardware vs SBusFPGA
gateware vs SBusFPGA
BYU_PYNQ_PR_Video_Pipeline_Hardware vs verilog-wishbone
gateware vs WARP_Core
BYU_PYNQ_PR_Video_Pipeline_Hardware vs satcat5
BYU_PYNQ_PR_Video_Pipeline_Hardware vs litex