swapforth

Swapforth is a cross-platform ANS Forth (by jamesbowman)

Swapforth Alternatives

Similar projects and alternatives to swapforth

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better swapforth alternative or higher similarity.

swapforth discussion

Log in or Post with

swapforth reviews and mentions

Posts with mentions or reviews of swapforth. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-06-15.
  • Making my own forth implementation
    5 projects | /r/Forth | 15 Jun 2023
  • FPGAs for interpreted programming languages?
    2 projects | /r/FPGA | 25 Nov 2022
  • How many LUT for an 8 bit CPU?
    2 projects | /r/FPGA | 11 Nov 2022
    Thanks! Found the port of this to the board I want :) https://github.com/jamesbowman/swapforth/tree/master/j1a
  • The RISC Deprogrammer
    2 projects | news.ycombinator.com | 28 Oct 2022
    It's a standard thing to do in EE curricula; you normally do it in a one-semester class, and there are literally thousands of open-source synthesizable CPU cores on GitHub now.

    To take two examples to show that designing a CPU is less work than writing a novel:

    - Chuck Thacker's "A Tiny Computer", fairly similar to the Nova, is a page and a half of synthesizable Verilog; it runs at 66 MHz in 200 LUTs of a Virtex-5: https://www.cl.cam.ac.uk/~swm11/examples/bluespec/Tiny3/Thac...

    - James Bowman's J1A is more like Chuck Moore's MuP21 and is about three pages of synthesizable Verilog: https://github.com/jamesbowman/swapforth/blob/master/j1a/ver... and https://github.com/jamesbowman/swapforth/blob/master/j1a/ver.... You can build it with Claire Wolf's iCEStorm (yosys, etc.) and run it on any but Lattice's tiniest FPGAs; it takes up 1162 4-input LUTs.

    I haven't quite done it myself. Last time I played https://nandgame.com/ it took me a couple of hours to play through the hardware design levels. But that's not really "design" in the sense of defining the instruction set (which is also kind of Nova-like), thinking through state machine design, and trying different pipeline depths; you're mostly just doing the kind of logic minimization exercises you'd normally delegate to yosys.

    In https://github.com/kragen/calculusvaporis I designed a CPU instruction set, wrote a simulator for it, wrote and tested some simple programs, designed a CPU at the RTL level, and sketched out gate-level logic designs to get an estimate of how big it would be. But I haven't simulated the RTL to verify it, written it down in an HDL, or breadboarded the circuit, so I'm reluctant to say that this qualifies as "designing a single CPU" either.

  • The J1 Forth CPU
    1 project | /r/Forth | 13 Jan 2021
    Also worth checking is the Swapforth Github repository.
  • A note from our sponsor - InfluxDB
    www.influxdata.com | 14 Jul 2024
    Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality. Learn more →

Stats

Basic swapforth repo stats
5
274
4.6
7 months ago

Sponsored
Power Real-Time Data Analytics at Scale
Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.
www.influxdata.com

Did you konow that Forth is
the 87th most popular programming language
based on number of metions?