vdf-fpga-round3-results
Results from the final round of the VDF competition focused on alternate constructions. (by supranational)
vdf-fpga
Implementation of an RSA VDF evaluator targeting FPGAs. (by supranational)
| vdf-fpga-round3-results | vdf-fpga | |
|---|---|---|
| 1 | 1 | |
| 3 | 46 | |
| - | - | |
| 0.0 | 0.0 | |
| about 4 years ago | over 4 years ago | |
| SystemVerilog | SystemVerilog | |
| GNU General Public License v3.0 or later | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
vdf-fpga-round3-results
Posts with mentions or reviews of vdf-fpga-round3-results.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-07-25.
vdf-fpga
Posts with mentions or reviews of vdf-fpga.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-07-25.