hammer vs siliconcompiler

hammer

Hammer: Highly Agile Masks Made Effortlessly from RTL (by ucb-bar)

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siliconcompiler

A modular build system for hardware (by siliconcompiler)

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docs.siliconcompiler.com

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hammer		siliconcompiler
	Project
2	Mentions	3
232	Stars	774
1.7%	Growth	3.2%
8.0	Activity	9.9
9 days ago	Latest Commit	about 11 hours ago
Python	Language	Python
BSD 3-clause "New" or "Revised" License	License	Apache License 2.0

The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

hammer

Posts with mentions or reviews of hammer. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-05-12.

Sunset TCL scripts ?
3 projects | /r/FPGA | 12 May 2023

It looks like there is a project to achieve similar goal but for ASIC tools https://github.com/ucb-bar/hammer
VLSI Tools
6 projects | /r/chipdesign | 14 Dec 2022

Hammer

siliconcompiler

Posts with mentions or reviews of siliconcompiler. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-12-14.

VLSI Tools
6 projects | /r/chipdesign | 14 Dec 2022

Silicon Compiler
VRoom A high end RISC-V implementation
4 projects | news.ycombinator.com | 21 Mar 2022
Siliconcompiler: Automate translation from source code to silicon
1 project | news.ycombinator.com | 11 Jan 2022

What are some alternatives?

When comparing hammer and siliconcompiler you can also consider the following projects:

OpenROAD - OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

OpenROAD-flow-scripts - OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

OSVVM-Scripts - OSVVM project simulation scripts. Scripts are tedious. These scripts simplify the steps to compile your project for simulation

riscv-isa-manual - RISC-V Instruction Set Manual

caravel_fulgor_opamp - Test Chip General Purpose OpAmp using Skywater SKY130 PDK

ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.