rvv-intrinsic-doc
riscv-v-spec
rvv-intrinsic-doc | riscv-v-spec | |
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6 | 43 | |
255 | 858 | |
2.7% | - | |
8.6 | 6.0 | |
3 days ago | about 2 months ago | |
C | Assembly | |
BSD 3-clause "New" or "Revised" License | Creative Commons Attribution 4.0 |
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rvv-intrinsic-doc
- Fixed length attributes · Issue #176 · riscv-non-isa/rvv-intrinsic-doc
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GCC 13.1 is now out... adds RVV vector intrinsics
Support for vector intrinsics as specified in version 0.11 of the RISC-V vector intrinsic specification, thanks Ju-Zhe Zhong from RiVAI for contributing most of implementation.
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RVV 1.0 assembly language example
The docs at https://github.com/riscv-non-isa/rvv-intrinsic-doc makes me think there should be a vfmacc_vv_f32m1_ta. I'll raise an issue there if it really is missing and not just me misunderstanding / using outdated stuff.
- Compiler Explorer supports RISC-V Clang with vector intrinsics
- Porting an AVX-512 neural net C99 code generator to RISC-V
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SQL on RISC-V Chip in Rust
If you're doing physics modeling or calculating light refractions or other stuff where you, a highly trained professional, have profiled and know that you'd benefit from V and the optimizer just isn't doing it, you can meet in the middle. The Vector Intrinsics are the contract between that highly trained professional and the compiler that aren't quite programming in assembly and handle the absurd avalanche (made easy by templates, but hard by C) of a templated/body that the optimizer can then easily inline without calling overhead and without blowing register allocation. It handles things like the generation of the 176 ways to find a maximum integer in an array. This is kind of the compromise between the autovectorization code not being able to decompose your nested Fortran loops or lighting effect in graphics or whatever but not quite reaching despair and coding it in assembly yourself. If you've ever programmed MMX, this will all look familiar.
riscv-v-spec
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Scaleway launches RISC-V servers
Here are some resources I can recommend:
RVV spec (also look at the examples in the repo): https://github.com/riscv/riscv-v-spec/blob/master/v-spec.ado...
RVV intrinsics viewer: https://dzaima.github.io/intrinsics-viewer
Tutorial: RISC-V Vector Extension Demystified (3 hour video going over every instruction): https://youtu.be/oTaOd8qr53U
RISC-V Vector extension in a nutshell: https://fprox.substack.com/p/risc-v-vector-extension-in-a-nu...
If you want to see a more complex example/real world application, then you might also be ibterested ib my article about vectorizing unicode conversions: https://camel-cdr.github.io/rvv-bench-results/articles/vecto...
In terms of development I'd recommend using qemu and a cross compiler, or if you want hardware try to get the kendryte k230 (currently the only sbc with rvv 1.0 support) or wait a bit for better hardware (BPI-F3 and sg2380 should release this year).
- Cray-1 performance vs. modern CPUs
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x86 vs ARM; Vector and Matrix Extensions; How do they compare?
And this isn't just some theoretical or something unlikely to happen - the official spec already contains such a bug. If the writers of the spec can't get things right, even with the small amount of code in the spec, I don't have high hopes that less informed programmers will. RVV being absurdly complicated (IMO, compared to SVE2 and AVX10) doesn't help its cause here.
- riscv64 is now an official Debian architecture (rebootstrap in progress)
- Vector vs SIMD
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LLVM's libc Gets Much Faster memcpy For RISC-V
Will the reference one actually be the most optimal one on future hardware?
- Is there any good place to find a copy-paste-able quick reference on RISC-V extensions? Particularly for the vector extension
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Building a toolchain suitable for compiling V extension code
I'll do a deep dive into the https://gms.tf/riscv-vector.html#getting-started tutorial, and probably pop the proverbial stack and just study RVV 0.7.1 on its own (using https://github.com/riscv/riscv-v-spec/releases/tag/0.7.1).
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A weird idea for using RV32E on a RV32I core - multithreaded microcontrollers?
I see your point. You can file a request for it at https://github.com/riscv/riscv-v-spec/issues if you want to pitch it to the relevant ISA bodies. The bar for implementing it pretty high.
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Examining the Top Five Fallacies About RISC-V
It's not "unusual"; using data registers for mask is a valid tradeoff especially for low-end implementations, whereas higher-end architectures can easily use shadow registers. Discussed in depth at https://github.com/riscv/riscv-v-spec/issues/811
What are some alternatives?
riscv-isa-sim - Spike, a RISC-V ISA Simulator
riscv-p-spec - RISC-V Packed SIMD Extension
rvv_example - Simple demonstration of using the RISC-V Vector extension
highway - Performance-portable, length-agnostic SIMD with runtime dispatch
highway - Highway - A Modern Javascript Transitions Manager
riscv-bitmanip - Working draft of the proposed RISC-V Bitmanipulation extension
vroom - VRoom! RISC-V CPU
learn-fpga - Learning FPGA, yosys, nextpnr, and RISC-V
meetings - WebAssembly meetings (VC or in-person), agendas, and notes
rvv-encoder - RISC-V V Extension Encoder
riscv-gnu-toolchain - GNU toolchain for RISC-V, including GCC
riscv-isa-manual - RISC-V Instruction Set Manual