riscv-v-spec
rvv-encoder
| riscv-v-spec | rvv-encoder | |
|---|---|---|
| 43 | 2 | |
| 858 | 0 | |
| - | - | |
| 6.0 | 0.0 | |
| about 2 months ago | almost 2 years ago | |
| Assembly | Rust | |
| Creative Commons Attribution 4.0 | - |
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riscv-v-spec
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Scaleway launches RISC-V servers
Here are some resources I can recommend:
RVV spec (also look at the examples in the repo): https://github.com/riscv/riscv-v-spec/blob/master/v-spec.ado...
RVV intrinsics viewer: https://dzaima.github.io/intrinsics-viewer
Tutorial: RISC-V Vector Extension Demystified (3 hour video going over every instruction): https://youtu.be/oTaOd8qr53U
RISC-V Vector extension in a nutshell: https://fprox.substack.com/p/risc-v-vector-extension-in-a-nu...
If you want to see a more complex example/real world application, then you might also be ibterested ib my article about vectorizing unicode conversions: https://camel-cdr.github.io/rvv-bench-results/articles/vecto...
In terms of development I'd recommend using qemu and a cross compiler, or if you want hardware try to get the kendryte k230 (currently the only sbc with rvv 1.0 support) or wait a bit for better hardware (BPI-F3 and sg2380 should release this year).
- Cray-1 performance vs. modern CPUs
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x86 vs ARM; Vector and Matrix Extensions; How do they compare?
And this isn't just some theoretical or something unlikely to happen - the official spec already contains such a bug. If the writers of the spec can't get things right, even with the small amount of code in the spec, I don't have high hopes that less informed programmers will. RVV being absurdly complicated (IMO, compared to SVE2 and AVX10) doesn't help its cause here.
- riscv64 is now an official Debian architecture (rebootstrap in progress)
- Vector vs SIMD
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LLVM's libc Gets Much Faster memcpy For RISC-V
Will the reference one actually be the most optimal one on future hardware?
- Is there any good place to find a copy-paste-able quick reference on RISC-V extensions? Particularly for the vector extension
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Building a toolchain suitable for compiling V extension code
I'll do a deep dive into the https://gms.tf/riscv-vector.html#getting-started tutorial, and probably pop the proverbial stack and just study RVV 0.7.1 on its own (using https://github.com/riscv/riscv-v-spec/releases/tag/0.7.1).
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A weird idea for using RV32E on a RV32I core - multithreaded microcontrollers?
I see your point. You can file a request for it at https://github.com/riscv/riscv-v-spec/issues if you want to pitch it to the relevant ISA bodies. The bar for implementing it pretty high.
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Examining the Top Five Fallacies About RISC-V
It's not "unusual"; using data registers for mask is a valid tradeoff especially for low-end implementations, whereas higher-end architectures can easily use shadow registers. Discussed in depth at https://github.com/riscv/riscv-v-spec/issues/811
rvv-encoder
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RISC-V V Extension Encoder
Since RISC-V "V" Vector Extension(RVV) not support in Rust yet. We made a function-like procedure macro called rvv_asm to write RVV inline assembly code in Rust. It parse the string literals line by line in the macro input and only translate RVV instruction and even the reserved RVV instrucntion to .byte {}, {}, {}, {} format instruction. We also provide a CLI tool rvv-as to translate RVV assembly source file.
What are some alternatives?
riscv-p-spec - RISC-V Packed SIMD Extension
rvemu - RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).
highway - Performance-portable, length-agnostic SIMD with runtime dispatch
rustsbi - RISC-V Supervisor Binary Interface (RISC-V SBI) library in Rust; runs on M or HS mode; good support for embedded Rust ecosystem. For binary download see https://github.com/rustsbi/standalone.
highway - Highway - A Modern Javascript Transitions Manager
riscv-rust - RISC-V processor emulator written in Rust+WASM
riscv-bitmanip - Working draft of the proposed RISC-V Bitmanipulation extension
rCore - Rust version of THU uCore OS. Linux compatible.
vroom - VRoom! RISC-V CPU
probe-rs - A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host
learn-fpga - Learning FPGA, yosys, nextpnr, and RISC-V
meetings - WebAssembly meetings (VC or in-person), agendas, and notes