rvv-encoder
rvemu
| rvv-encoder | rvemu | |
|---|---|---|
| 2 | 6 | |
| 0 | 706 | |
| - | - | |
| 0.0 | 1.9 | |
| almost 2 years ago | 3 months ago | |
| Rust | Rust | |
| - | MIT License |
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rvv-encoder
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RISC-V V Extension Encoder
Since RISC-V "V" Vector Extension(RVV) not support in Rust yet. We made a function-like procedure macro called rvv_asm to write RVV inline assembly code in Rust. It parse the string literals line by line in the macro input and only translate RVV instruction and even the reserved RVV instrucntion to .byte {}, {}, {}, {} format instruction. We also provide a CLI tool rvv-as to translate RVV assembly source file.
rvemu
- Suggested Resources to Learn how to Write RISCV Emulator?
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RVVM – The RISC-V Virtual Machine
More emulators lists here:
https://riscv.org/exchange/software/
The most popular ones are qemu and spike. There are even a few emulators written in Rust that aren't on the list:
https://github.com/shady831213/terminus
https://github.com/d0iasm/rvemu
I've messed around with Terminus the most.
- RISC-V online/CLI emulator written in Rust (supports RV64IMAFD, peripherals and more)
What are some alternatives?
riscv-v-spec - Working draft of the proposed RISC-V V vector extension
RVVM - The RISC-V Virtual Machine
rustsbi - RISC-V Supervisor Binary Interface (RISC-V SBI) library in Rust; runs on M or HS mode; good support for embedded Rust ecosystem. For binary download see https://github.com/rustsbi/standalone.
probe-rs - A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host
riscv-rust - RISC-V processor emulator written in Rust+WASM
rCore - Rust version of THU uCore OS. Linux compatible.
gopher64 - N64 emulator written in Rust
riscv_em - Simple risc-v emulator, able to run linux, written in C.
terminus - A riscv isa simulator in rust.
psx-rs - Playstation emulator written in Rust