riscv-sbi-doc
nytm-spelling-bee
| riscv-sbi-doc | nytm-spelling-bee | |
|---|---|---|
| 5 | 2 | |
| 316 | 32 | |
| 2.2% | - | |
| 7.5 | 0.0 | |
| 26 days ago | about 5 years ago | |
| Makefile | C++ | |
| Creative Commons Attribution 4.0 | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-sbi-doc
-
RISC-V SBI and the full boot process
The SBI spec[0] is not a long read.
0. https://github.com/riscv-non-isa/riscv-sbi-doc/releases
-
ARM or x86? ISA Doesn’t Matter
>What does matter is standardization. For example a booting process.
Truth.
This is why RISC-V put a lot of effort on this, and put it early.
Relevant specs include but isn't limited to SBI[0], UEFI protocol[1] and the ongoing platform specification[2].
0. https://github.com/riscv-non-isa/riscv-sbi-doc/releases
1. https://github.com/riscv-non-isa/riscv-uefi/releases/tag/1.0...
2. https://github.com/riscv/riscv-platform-specs
-
HiFive Unmatched – A RISC-V Linux development platform
Well that's a very good question. At the moment the reality is something of a mess, because someone looked at Arm and though that must be a good idea. Plus the RISC-V Foundation has even less control over implementers than Arm does (which doesn't have a lot).
The good news is that the foundation is defining various platform specs. For servers it'll include a standard firmware spec plus open source firmware implementation and a few other bits. Maybe working UEFI one day. (https://lists.riscv.org/g/tech-unixplatformspec https://github.com/riscv-non-isa/riscv-sbi-doc)
-
what is EEI, AEE, SEE, SBI? How do they all fit together?
The SBI (Supervisor-Binary Interface) is the API used by S-mode software (your operating system) to communicate with M-mode, and abstract away some hardware-specific details. It handles things like communicating between harts, power management, and performance monitoring. On real hardware, it is implemented by M-mode software. For VMs, it is typically implemented by the hypervisor. It's roughly analogous to the PSCI in ARM. For more information, have a look at the spec.
nytm-spelling-bee
- HiFive Unmatched – A RISC-V Linux development platform
-
Do Low-Level Optimizations Matter?
If you are designing a sorting algorithm component for production, it is critical to take into account all the blips and wrinkles that real components will face.
But when you are investigating how and why your CPU has the performance characteristics it has evolved, all those complications directly interfere with learning. The goal here was not to make a production-grade sorting tool; it was to understand what affects performance, using the sorting problem as a microscope.
The method is generally useful. Some years back I spent months refining a one-page program[1] to generate a list of word puzzles. After the first day, the list of puzzles was of no interest, but refining the means to produce it faster taught me a great deal.
[1] https://github.com/ncm/nytm-spelling-bee
What are some alternatives?
riscv-bitmanip - Working draft of the proposed RISC-V Bitmanipulation extension
riscv-uefi
pdqsort - Pattern-defeating quicksort.
vroom - VRoom! RISC-V CPU
ips4o - In-place Parallel Super Scalar Samplesort (IPS⁴o)
riscv-acpi
riscv-bringup - Risc-V journey thru containers and new projects
riscv-platform-specs - RISC-V Profiles and Platform Specification