riscv-isa-manual
ghidra
riscv-isa-manual | ghidra | |
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41 | 126 | |
3,293 | 47,762 | |
2.6% | 1.7% | |
9.7 | 10.0 | |
3 days ago | 7 days ago | |
TeX | Java | |
Creative Commons Attribution 4.0 | Apache License 2.0 |
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riscv-isa-manual
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The Improved RISC-V Specification (latest WIP draft)
https://github.com/riscv/riscv-isa-manual/releases
Regarding the recent "How to improve the RISC-V specification" post [0], I just wanted to point out, that the latest draft manual is already a great improvement. (see link above)
It includes a lot of the newly ratified extensions: bitmanip,zicond,vector,vector crypto, ...
And there are a bunch of included SAIL definitions for bitmanip and zicond, but other instructions are still missing the SAIL code. Most notably, the SAIL definitions from the RV32I/RV64I base isa are also missing.
I asked for the further SAIL integration plans here: https://github.com/riscv/riscv-isa-manual/issues/1369
Here is an example SAIL snippet from cpopw:
let bitcount = 0;
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How to improve the RISC-V specification
I encourage you to look at the newest isa manual draft on github: https://github.com/riscv/riscv-isa-manual/releases
It includes the more recently extensions, and e.g. the bitmanip instructions all have associated pseudo code.
Here is e.g. the code for cpopw:
let bitcount = 0;
- Need help with designing a basic RISC V processor?
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The legend of “x86 CPUs decode instructions into RISC form internally”
I tried searching the spec [1] for "overflow" and here is what it says at page 17:
> We did not include special instruction-set support for overflow checks on integer arithmetic operations in the base instruction set, as many overflow checks can be cheaply implemented using RISC-V branches.
> For general signed addition, three additional instructions after the addition are required
Is this "cheap", replacing 1 instruction with four? According to some old mainframe era research (cannot find link now), addition is the most often used instruction and they suggest that we should replace each one with four?
Their "rationale" is not rational at all. It doesn't make sense.
Overflow check should be free (no additional instructions required), otherwise we will see the same story we have seen for last 50 years: compiler writers do not want to implement checks because they are expensive; language designers do not want to use proper arithmetic because it is expensive. As a result, there will be errors and vulnerabilities. A vicious circle.
[1] https://github.com/riscv/riscv-isa-manual/releases/download/...
- 64-bit Arm ∩ 64-bit RISC V
- Beginner question: F extension
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Riscv Ghidra Instruction Manual
Why not use the actual release PDF instead from their github? https://github.com/riscv/riscv-isa-manual
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How would I go about designing an 8-bit RISC-V CPU? Is it possible?
https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf Part 2
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Have to convert a C language code into RISC-V MIPS
If you don't want to cheat then read the RISC-V ISA manual: https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf
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How does a computer understand machine language?
Yeah you are on the right track. Processors are designed on top of an Instruction Set Architecture (ISA). For an example you can look on top of the RISC-V specifications:https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf (possible PDF download)
ghidra
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TryHackMe- Compiled
Let's see what our beloved software reverse engineering framework Ghidra has to show.
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OpenAI is working with the US military now
Define war machinery. Contributing to Ghidra?
https://github.com/NationalSecurityAgency/ghidra
- Ghidra 11.0 Released
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Dogbolt Decompiler Explorer
Binary Ninja likewise is empty and keeps up just fine as well. It's not a coincidence that the two commercial products that are funding it are both confident enough to put their stuff online like this.
And it's no conspiracy theory or intentional sandbagging, you can see the implementation: https://github.com/decompiler-explorer/decompiler-explorer
and if anyone can improve the other tools performance we'd be happy to accept it. We reached out to the Ghidra devs: https://github.com/NationalSecurityAgency/ghidra/issues/5228 but they didn't have any silver bullets for us either.
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Show HN: Ghidra Plays Mario
Nice, I'll give it a closer look. My only concern so far is memory hooking (still needed for hardware registers), which on Java side was called by FilteredMemoryState [1]. In memstate.cc it looks like just the simpler MemoryState is implemented [2], and there's no equivalent to MemoryAccessFilter. But it might not be that complicated to add...
[1]: https://github.com/NationalSecurityAgency/ghidra/blob/4561e8...
[2]: https://github.com/NationalSecurityAgency/ghidra/blob/4561e8...
- NSA releases Ghidra version 10.3.3
- Ghidra 10.3.2 released!
- Ghirda 10.3.2 released!
- Debugger Ghidra Class
What are some alternatives?
riscv-elf-psabi-doc - A RISC-V ELF psABI Document
x64dbg - An open-source user mode debugger for Windows. Optimized for reverse engineering and malware analysis.
riscv-emulator-docker-image
cutter - Free and Open Source Reverse Engineering Platform powered by rizin
amaranth - A modern hardware definition language and toolchain based on Python
rizin - UNIX-like reverse engineering framework and command-line toolset.
riscv-v-spec - Working draft of the proposed RISC-V V vector extension
r2ghidra - Native Ghidra Decompiler for r2
vroom - VRoom! RISC-V CPU
ret-sync - ret-sync is a set of plugins that helps to synchronize a debugging session (WinDbg/GDB/LLDB/OllyDbg2/x64dbg) with IDA/Ghidra/Binary Ninja disassemblers.
open-source-cs - Video discussing this curriculum:
ghidra-dark - Dark theme installer for Ghidra