rCore
rvv-encoder
| rCore | rvv-encoder | |
|---|---|---|
| 2 | 2 | |
| 3,338 | 0 | |
| 1.1% | - | |
| 2.5 | 0.0 | |
| 8 months ago | almost 2 years ago | |
| Rust | Rust | |
| MIT License | - |
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rCore
- Ask HN: Examples of Microkernels?
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Is there a book or source that teaches Operating System concepts such as Multi-Process, Signal, File System and mmap in Rust?
Tsinghua university offers a OS course with their OS written in rust. https://github.com/rcore-os/rCore. I haven't checked out the content myself but have heard really good words about it.
rvv-encoder
-
RISC-V V Extension Encoder
Since RISC-V "V" Vector Extension(RVV) not support in Rust yet. We made a function-like procedure macro called rvv_asm to write RVV inline assembly code in Rust. It parse the string literals line by line in the macro input and only translate RVV instruction and even the reserved RVV instrucntion to .byte {}, {}, {}, {} format instruction. We also provide a CLI tool rvv-as to translate RVV assembly source file.
What are some alternatives?
octox - Unix-like OS in Rust inspired by xv6-riscv
riscv-v-spec - Working draft of the proposed RISC-V V vector extension
novusk - A kernel written in Rust
rvemu - RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).
xv6-riscv - Xv6 for RISC-V
rustsbi - RISC-V Supervisor Binary Interface (RISC-V SBI) library in Rust; runs on M or HS mode; good support for embedded Rust ecosystem. For binary download see https://github.com/rustsbi/standalone.
qubes-mirage-firewall - A Mirage firewall VM for QubesOS
riscv-rust - RISC-V processor emulator written in Rust+WASM
moros - MOROS: Obscure Rust Operating System 🦉
probe-rs - A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host
cross - “Zero setup” cross compilation and “cross testing” of Rust crates
composite - A component-based OS