r5lite
By specbranch
component-template
General SystemVerilog Component Development Template (by NYU-Processor-Design)
| r5lite | component-template | |
|---|---|---|
| 2 | 1 | |
| - | 0 | |
| - | - | |
| - | 3.9 | |
| - | 3 months ago | |
| CMake | ||
| - | Creative Commons Zero v1.0 Universal |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
r5lite
Posts with mentions or reviews of r5lite.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-03-07.
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Launch HN: SiLogy (YC W24) – Chip design and verification in the cloud
It's not in gitlab's CI infrastructure, but I have continuous integration set up in a private server for https://gitlab.com/specbranch/r5lite and also for my company's proprietary hardware.
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Recommendations for RISC-V on FPGA
I wish I could recommend the one I am working on open-sourcing, but it's not exactly ready yet for a school project (shameless plug for the future: https://gitlab.com/specbranch/r5lite/) unless you are doing something very basic solely inside the core.
component-template
Posts with mentions or reviews of component-template.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-03-07.
-
Launch HN: SiLogy (YC W24) – Chip design and verification in the cloud
The functionality on offer here is equivalent to about 30 lines of Github Actions YAML to install verilator, run the tests, and upload the coverage information. [1]
Generating waveforms is free, Verilator already does that if you pass it the appropriate argument, either --trace or --trace-fst. We usually control that with a single CMake option.
Complex workflows can get nutty, but what's illustrated here is not a complex workflow.
[1]: https://github.com/NYU-Processor-Design/component-template/b...
What are some alternatives?
When comparing r5lite and component-template you can also consider the following projects:
iob-soc - RISC-V System on Chip Template
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
PurdNyUart