nerv
Naive Educational RISC-V -- A simple single-stage RV32I processor (by SymbioticEDA)
16bit_Risc_Processor
A 16 bit Risc Processor using VHDL. (by mgmokdad)
| nerv | 16bit_Risc_Processor | |
|---|---|---|
| 1 | 2 | |
| 23 | 1 | |
| - | - | |
| 0.0 | 3.6 | |
| over 3 years ago | over 3 years ago | |
| SystemVerilog | VHDL | |
| GNU General Public License v3.0 or later | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
nerv
Posts with mentions or reviews of nerv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-02-09.
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Where to start if I want to build a RISC-V instruction set in verilog from scratch?
Here is a formally verified, single-cycle RISC-V implementation in Verilog: nerv
16bit_Risc_Processor
Posts with mentions or reviews of 16bit_Risc_Processor.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-02-09.