logisim-evolution VS hardcaml

I have downloaded logisim-evolution from github. While trying to run .msi file, Microsoft Defender blocked it for some reason. I scanned it with some other scanners and everything was fine. I'm not sure if this is safe to install it.

I am trying to define an xbps-src template for logisim-evolution, a Java app that requires Java 16. I am using depends="virtual?java-runtime" and, as expected by reading etc/defaults.virtual, OpenJDK 8 is used. Creating a etc/virtual file is ignored in .gitignore, so I guess it is made to be used with local packages. Using depends="virtual?java-runtime-17.0.5+7_1" works, as OpenJDK 17 provides that exact version of java-runtime. If it were updated, this package would break, because if I input a lower version, it will fail. I've tried using syntax like > and >=, but then I get the following error:

Logism evolution works great and is quite modern.

https://github.com/logisim-evolution/logisim-evolution

According to Logisim it creates the correct sequence for full stepping on a bipolar configuration. Falstad's Circuit simulator is another one you might try.

Did you check logisim-evolution? It is an active fork of logisim maintained by several lecturers at the Bern University of Applied Sciences.

Here is the link for Logisim Evolution: https://github.com/logisim-evolution/logisim-evolution

In school, I worked on an introductory CS/EE class many, many moons ago, and I believed we used something like "logisim", which by then was pretty awesome - you could build simple things like adders, combine those with "macros" to bui;d ALUs and then whole simple CPUs.

Since then, the logisim project has discontinued, but it looks like there is a open source successor:

https://github.com/logisim-evolution/logisim-evolution

Have not tried it, but it looks promising, provided you don't want to do too complicated things (not sure if you could really model complex CPUs like a pentium with it). Also, it's pretty digital only, so I wouldn't expect Mac-Spice-like analog circuit simulation.

though i'd heavily recommend first building the circuit in a logic simulator like Logisim, or Digital before trying to build it in a game for an FPGA. (Digital even allows you to export circuits as Verilog/VHDL, and as a certified lazy person, that is very useful)

Logisim-evolution An alternative free and open-source tool to design and simulate digital logic.

See if you are comfortable playing in https://github.com/logisim-evolution/logisim-evolution

title: Accelerating zk-SNARKs - MSM and NTT algorithms on FPGAs with Hardcaml

Any reason the title deviates so much from original? Is it because of all the cool acronyms and code words? Here's a decoder:

zk-SNARK: zero-knowledge Succinct Non-Interactive Argument of Knowledge

MSM: Multi-Scalar Multiplication

Hardcaml: OCaml lib for hardware: https://github.com/janestreet/hardcaml

NTT: Number Theoretic Transform

Perhaps peripheral (the original site has been hugged to death).

Both clashlang: https://clash-lang.org/

And Hardcaml: https://github.com/janestreet/hardcaml

have personally fueled my interest in hardware.

Dan Luu speaks eloquently and at length about how better options are needed for logic design. I would recommend both of the above to the enthusiastic novice.

Join JS and you can program FPGAs in a strongly typed, expressive, high level programming language (OCaml): https://github.com/janestreet/hardcaml

[1] https://github.com/janestreet/hardcaml

> You can put all the functions/tasks you want in that module.

Coming from a software background, the testing strategies available in Verilog seem very clunky and overly verbose. In comparison, Hardcaml's ASCII waveform expect-test solution feels extremely elegant and simple: https://blog.janestreet.com/using-ascii-waveforms-to-test-ha....

> And all of my development and that of my team happens through gitlab-CI.

That's probably more of a gap in my education than a fault of the ecosystem then.

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Among other qualities, I prefer languages that let fewer mistakes slip through, and allow the developer to focus on the system they intend to build rather than avoiding bugs/misunderstandings that would be easy to catch otherwise. You bring up a lot of really good points, and I suspect that if we were doing Verilog "the right way", we would have probably run into fewer issues. But at the end of the day, developing in Hardcaml was a much more ergonomic experience: testing was straightforward, most "stupid mistakes" were impossible, setup was pretty easy, and the library provided a lot of really useful abstractions. For example, Hardcaml interfaces make it easy to represent practically any data structure that can be serialized to/from a bit vector, and the Always API allows for some pretty interesting non-trivial functional logic.

https://github.com/janestreet/hardcaml/blob/master/docs/hard...

A few months ago, I came across the Signals and Threads Programmable Hardware episode. I really liked the idea of Hardcaml: a library to write and test hardware designs in OCaml. Representing circuits as functions felt like a good abstraction, and I’ve been wanting to learn OCaml for a while.