vISA
ao486_MiSTer
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| vISA | ao486_MiSTer | |
|---|---|---|
| 19 | 21 | |
| - | 235 | |
| - | 1.3% | |
| - | 5.8 | |
| - | 9 days ago | |
| Verilog | ||
| - | GNU General Public License v3.0 or later |
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vISA
- My Six Lines of Verilog Code Turing Complete BitBitJump Is Now Under the GPLv3
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1-bit CPU for 'super low-performance computer' launched – sells out promptly
Speed test against my six lines of verilog cpu when? *
https://gitlab.com/VitalMixofNutrients/vISA
* Only six lines of verilog if one only uses FPGA LUTs as Ram.
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Hey I'm genuinely curious about what makes you guys like working.
Well, I made a CPU Instruction Set Architecture called Bit-Bit-Jump that can simulate Bit-Bit-Jump Machine Code at approximately 5.6 Megahertz here: https://gitlab.com/VitalMixofNutrients/vISA
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What is easier for programmers to understand? An entire program that was written in one source code file, or an entire directory of source code files getting statically / dynamically linked into an entire program?
Hello. Over the past six months, I have been working on a CPU ISA named Bit-Bit-Jump. Suprisingly, it is actually the world's simplest CPU ISA, comprising only SIX lines of Verilog code.
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Error: Unsupported tristate construct (not in propagation graph):
You're right, it doesn't look like an actual binary.. How can I turn it into an actual binary?
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What is your take on ISA architectures for FPGAs (x86, arm, risc-v)?
Well, the simplest ISA is six lines of Verilog and it's called Bit-Bit-Jump
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MSc thesis topic advice related with fpga.
Idea: Because I don't have the money for Vivado (Free version is limited to a few thousand lines of Verilog) / Quartus (Free version won't let me perform DPR), it would be awesome if you could find a way to implement my Bit-Bit-Jump Soft-Core into your project. Here's my project: https://gitlab.com/VitalMixofNutrients/vISA (Licensed under GPLv2 Only.)
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When you implement an CPU ISA (Bit-Bit-Jump) in only six lines of Verilog:
My BBJ code is available here: https://gitlab.com/VitalMixofNutrients/vISA/-/raw/vISA/sources/sim/verilator/BBJ/BBJ.v (Licensed under GPLv2 only.)
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What architecture is the most chad?
Bit-Bit-Jump.
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Anon can't get a job
(My coding project in question: https://gitlab.com/VitalMixofNutrients/vISA)
ao486_MiSTer
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Reverse engineering the Intel 386 processor's register cell
How about a 486 instead? :)
https://github.com/MiSTer-devel/ao486_MiSTer
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Issues with AO486
Have you checked all the details in https://github.com/MiSTer-devel/ao486_MiSTer ?
- Ao486_MiSTer: i486 core for the MiSTer FPGA gaming system
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Recently, I came across a video on Youtube by Linus Tech Tips about the PCEm emulator that I found to be cringy and ill-informed. As a computer engineer by education let me explain few core concepts on how emulation works.
You mention "Pentium MMX CPU" a few times in your post, but fail to mention any FPGA solution that can emulate a machine of that class. MiSTer can't do that, the best it can do is a 486 (not just missing MMX, doesn't even have an FPU).
- Exact 486 CPU Performance in Smallest Form Factor
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Emulate Any ISA Card With A Raspberry Pi And An FPGA
It has already happened: https://github.com/MiSTer-devel/ao486_MiSTer
- Are there FPGA cores for SB16/ET4KW32/NE2K?
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KEYBCS2
The last processor generation it worked on is the 486, but on a Pentium or newer it always fails with a “Debugging is not allowed” message.
I guessed the reason for that correctly - prefetch queue. Mentions of CUP386 in the comments also brought back more memories of the cracking scene in the late 80s/early 90s. There's some very interesting discussion on SMC vs CPU behaviour here --- in the context of an open-source 486-level SoC core:
https://github.com/MiSTer-devel/ao486_MiSTer/issues/33
What are some alternatives?
microwatt - A tiny Open POWER ISA softcore written in VHDL 2008
dosbox-x - DOSBox-X fork of the DOSBox project
VexRiscvBPluginGenerator
PCem-ROMs - This is a collection of requiered ROMs files for PCem emulator. RIP PCem 2021
verilator - Fork of Verilator with prebuilt Ubuntu binaries (https://www.veripool.org/wiki/verilator)
elks - Embeddable Linux Kernel Subset - Linux for 8086
dcc - Dan's C compiler
libi86 - Attempt to reimplement non-standard C library facilities (e.g. <conio.h>) used in MS-DOS programs, for IA-16 GCC & ACK ― mirror of https://gitlab.com/tkchia/libi86 • Ubuntu packages for cross-compilation at https://launchpad.net/%7Etkchia/+archive/ubuntu/build-ia16/ • DJGPP/MS-DOS binaries at https://github.com/tkchia/libi86/releases
Smallpond - Brand new RISC architecture created in CSE 490
NyuziProcessor - GPGPU microprocessor architecture
beri - The BERI and CHERI processor and hardware platform