vISA VS VexRiscvBPluginGenerator

Speed test against my six lines of verilog cpu when? *

https://gitlab.com/VitalMixofNutrients/vISA

* Only six lines of verilog if one only uses FPGA LUTs as Ram.

Well, I made a CPU Instruction Set Architecture called Bit-Bit-Jump that can simulate Bit-Bit-Jump Machine Code at approximately 5.6 Megahertz here: https://gitlab.com/VitalMixofNutrients/vISA

Hello. Over the past six months, I have been working on a CPU ISA named Bit-Bit-Jump. Suprisingly, it is actually the world's simplest CPU ISA, comprising only SIX lines of Verilog code.

You're right, it doesn't look like an actual binary.. How can I turn it into an actual binary?

Well, the simplest ISA is six lines of Verilog and it's called Bit-Bit-Jump

Idea: Because I don't have the money for Vivado (Free version is limited to a few thousand lines of Verilog) / Quartus (Free version won't let me perform DPR), it would be awesome if you could find a way to implement my Bit-Bit-Jump Soft-Core into your project. Here's my project: https://gitlab.com/VitalMixofNutrients/vISA (Licensed under GPLv2 Only.)

My BBJ code is available here: https://gitlab.com/VitalMixofNutrients/vISA/-/raw/vISA/sources/sim/verilator/BBJ/BBJ.v (Licensed under GPLv2 only.)

Bit-Bit-Jump.

(My coding project in question: https://gitlab.com/VitalMixofNutrients/vISA)

I'd say beyond availability, the primary advantage for embedded use it the adaptability of the ISA. If you just need a small microcontroller, the core can be very small; if you need some specific performance point, you can use a bigger core, some extensions (or part thereof) could help, and you can always roll your own instructions in the 'custom' opcode space to reach your goals.