chisel-book
Digital Design with Chisel (by schoeberl)
mr1
MR1 formally verified RISC-V CPU (by tomverbeure)
chisel-book | mr1 | |
---|---|---|
4 | 2 | |
699 | 47 | |
- | - | |
8.1 | 10.0 | |
11 days ago | over 5 years ago | |
TeX | Scala | |
- | The Unlicense |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
chisel-book
Posts with mentions or reviews of chisel-book.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-01-08.
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Lua on an FPGA
If you do your work in Chisel the creator of JOP also wrote a book on Chisel, then you might be able to get some free advice along the way, :)
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Which you woukd choose between SpinalHDL, Chisel or Clash as begineer?
Chisel likely has the largest user base of these three and should also be the most mature because of this. There is a book to go with it https://github.com/schoeberl/chisel-book.
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What do think of Chisel HDL? is it worth learning over Verilog/SystemVerilog?
Sure. You can follow this little .pdf: https://github.com/schoeberl/chisel-book
- Silice: A language for hardcoding Algorithms into FPGA hardware
mr1
Posts with mentions or reviews of mr1.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-01-08.
-
Which you woukd choose between SpinalHDL, Chisel or Clash as begineer?
I also wrote a small RISC-V CPU with it. Same philosophy: Verilog replacement, no advanced features. Code is here. I don't even use the SpinalHDL FSM features.
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So what's the deal with CHISEL, and why is it so great?
I look at the RTL of my toy CPU that doesn’t use any advanced SpinalHDL techniques, and I think that almost anyone who can read Verilog would pick up in an instant what it’s doing. For RTL, I just don’t any benefits in using Verilog instead…
What are some alternatives?
When comparing chisel-book and mr1 you can also consider the following projects:
Silice - Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
tensil - Open source machine learning accelerators
Rosebud - Framework for FPGA-accelerated Middlebox Development