chips VS PostgreSQL

Because it's a software implementation in Verilog which is much closer to a software emulator and has nothing to do with the original Z80 "transistor structure".

For instance here's the LD A,(DE) "payload":

https://github.com/rejunity/z80-open-silicon/blob/974c7711b2...

And here's the equivalent in my software emulator:

https://github.com/floooh/chips/blob/bd1ecff58337574bb46eba5...

What's interesting though is that the Verilog implementation doesn't seem to update the internal WZ register, even though there are references to WZ in other places.

But in the end, if it looks and feels like a Z80 from the outside (e.g. the right pins are active at the right time) the internal implementation doesn't matter all that much.

Author here, interesting to see this posted since it's more like a reference manual for Z80 instructions with 'unusual' timings. The followup blog post about the cycle-stepped Z80 emulator is probably more interesting:

https://floooh.github.io/2021/12/17/cycle-stepped-z80.html

One important note: at the start of the post I'm speculating about why I was seeing some minor differences to a 'real' Z80, it turned out that this speculation was wrong and instead the differences were caused by 'incomplete' netlist simulation code which worked fine for the 6502 but required some tweaks for the Z80, see the comments of this GH issue for details: https://github.com/floooh/v6502r/issues/2.

As far as I'm aware the netlist simulation now behaves correctly like a Zilog Z80 (but note that reverse engineered Z80 clones like the East German U880 are known to have slightly different undocumented behaviour), and the Z80 emulator in https://github.com/floooh/chips is tested against the netlist simulation for correct behaviour and timing.

I simply don't see that there's a big enough difference between traditional garbage collection, refcounting and manual memory management. Each of those can already be implemented in pure WASM, just more or less awkwardly.

As for "just another ISA", there have been CPUs which had separate call- and data-stacks, with the call-stack living on the CPU and not accessible as regular data. In that sense WASM isn't much different then those esoteric CPUs.

And even though WASM might not allow free jumps, I yet have to see a noticeable performance difference between WASM and native for this type of "worst case code":

https://github.com/floooh/chips/blob/f5b6684ff6e899429544b21...

Oh my, the 6502 emulation [1] has fewer lines of assembly code than my (code-generated) implementation has lines of C code [2] :D

Very nice use of a macro assembler though [3], makes the code feel very high level.

To my defense, the generated code has a lot of redundancies (such as assert(false) which were meant to catch any 'stray cycles' but which are removed in release mode.

[1] https://github.com/zajo/appler/blob/develop/src/65C02.ASM

[2] https://github.com/floooh/chips/blob/master/chips/m6502.h

[3] https://github.com/zajo/appler/blob/52aaa0f768cdf303438cd2c7...

I don't know if it's the best code I've ever read but this emulation library [0] of 8 bits computers is pretty well written, documented and designed: https://github.com/floooh/chips.

It's a good way to document old hardware with emulation code.

Looks like here's the source code of the emulators:

8-bit chip and system emulators in standalone C headers - https://github.com/floooh/chips

There's a project on GitHub of similar nature -- it has include-able .h files emulating 8-bit computer chips on the pin level, and bus state is also held in a 64-bit value: https://github.com/floooh/chips/blob/master/chips/m6502.h

I wrote also a library of components for some complex chips (like 6502 simulation using https://github.com/floooh/chips)

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