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Author here, interesting to see this posted since it's more like a reference manual for Z80 instructions with 'unusual' timings. The followup blog post about the cycle-stepped Z80 emulator is probably more interesting:
https://floooh.github.io/2021/12/17/cycle-stepped-z80.html
One important note: at the start of the post I'm speculating about why I was seeing some minor differences to a 'real' Z80, it turned out that this speculation was wrong and instead the differences were caused by 'incomplete' netlist simulation code which worked fine for the 6502 but required some tweaks for the Z80, see the comments of this GH issue for details: https://github.com/floooh/v6502r/issues/2.
As far as I'm aware the netlist simulation now behaves correctly like a Zilog Z80 (but note that reverse engineered Z80 clones like the East German U880 are known to have slightly different undocumented behaviour), and the Z80 emulator in https://github.com/floooh/chips is tested against the netlist simulation for correct behaviour and timing.
Author here, interesting to see this posted since it's more like a reference manual for Z80 instructions with 'unusual' timings. The followup blog post about the cycle-stepped Z80 emulator is probably more interesting:
https://floooh.github.io/2021/12/17/cycle-stepped-z80.html
One important note: at the start of the post I'm speculating about why I was seeing some minor differences to a 'real' Z80, it turned out that this speculation was wrong and instead the differences were caused by 'incomplete' netlist simulation code which worked fine for the 6502 but required some tweaks for the Z80, see the comments of this GH issue for details: https://github.com/floooh/v6502r/issues/2.
As far as I'm aware the netlist simulation now behaves correctly like a Zilog Z80 (but note that reverse engineered Z80 clones like the East German U880 are known to have slightly different undocumented behaviour), and the Z80 emulator in https://github.com/floooh/chips is tested against the netlist simulation for correct behaviour and timing.