PSX
gb-test-roms
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| PSX | gb-test-roms | |
|---|---|---|
| 3 | 17 | |
| 103 | 429 | |
| - | 4.0% | |
| 0.0 | 0.0 | |
| almost 4 years ago | almost 9 years ago | |
| Assembly | Assembly | |
| - | - |
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PSX
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Noctane: WIP PSX emulator
I am using the tests from here: https://github.com/PeterLemon/PSX
- What's everyone currently working on?
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Duckstation got an update
Games shown are: - Hover Racing: http://www.psxdev.net/forum/viewtopic.php?t=636 - Fromage: https://chenthread.asie.pl/fromage/ - PSXNICCC Demo: https://github.com/PeterLemon/PSX/tree/master/Demo/PSXNICCC
gb-test-roms
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What's everyone working on?
Make sure you incorporate testing your implementation with test roms: https://github.com/retrio/gb-test-roms Do this as early in the project as possible. This will save you a huge migraine later on.
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Some GameBoy games running at half speed
Have you tested your emulator against blargg's instruction timing test ROM? I believe this one only checks cycle counts, not memory timings: https://github.com/retrio/gb-test-roms/tree/master/instr_timing
- Need some help on how to progress with my gameboy emulator after opcodes.
- Getting weird desync on Super Mario Land (GB) between the attract mode and real gameplay. Any ideas?
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Me again... Blarg's Gameboy test ROM
Yeah the source for cpu_instrs is in github. https://github.com/retrio/gb-test-roms/tree/master/cpu_instrs/source
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What memory address do I load Blaargs test ROMs into? Is it 0x0100?
I actually have a question about this. I've been building a Gameboy emulator, the CPU works but when it runs the RET instruction the PC jumps to some really high address like 0x2000 or something when it's meant to jump to somewhere around 0x400 instead (after comparing it with another GB emulator). I think the RET address is meant to be read from HRAM, where the stack is stored, but when I look there it is the value around 0x2000 like I mentioned earlier. Are there any special quirks with this section of memory that I might not have implemented? I'm pretty much just reading and writing from an array for HRAM at the moment. I'm having the issue on one of blarggs cpu-instrs test roms https://github.com/retrio/gb-test-roms/blob/master/cpu_instrs/cpu_instrs.gb
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Best documentation for the details?
So just start with implementing the CPU's fetch/decode/execute loop and a rudimentary memory bus, so that you can run simple test ROMs. You don't even need a display for many test ROMs (like Blargg's well-known test suite, which writes the results to the serial port as well as the display). After that you can do test-driven development (in a way) and focus on making more and more tests pass. Don't worry about details until you need to.
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Gameboy emulator blargg test 02 EI failed #2
It looks like the test enables interrupts and then invokes the timer interrupt.
- Gameboy Blargg test 03 - Infinite loop
- [GameBoy] Problem with CD instruction.
What are some alternatives?
temu-vsb - TEMU ("Tandy Emulator") and VSB ("Virtual Sound Blaster"), two nifty MS-DOS TSR utilities originally developed by Andrew Zabolotny (Андрей Заболотный).
mooneye-gb - A Game Boy research project and emulator written in Rust
gba-tests - A collection of Game Boy Advance tests.
jitboy - A Game Boy emulator with dynamic recompilation (JIT)
DK86PC - A WIP Intel 8086 and IBM PC 5150 emulator.
Ryujinx - Experimental Nintendo Switch Emulator written in C#
GBA - Game Boy Advance Bare Metal Assembly Programming
dmg-acid2 - 😀 The Acid2 test, now for the original Game Boy! 😀
nes-test-roms - Collection of test ROMs for testing a NES emulator.
decaf-emu - Researching Wii U emulation.
Projects - Ted Fried's MicroCore Labs Projects which include microsequencer-based FPGA cores and emulators for the 8088, 8086, 8051, 6502, 68000, Z80, Risc-V, and also Typewriter and EPROM Emulator projects. MCL51, MCL64, MCL65, MCL65+, MCL68, MCL86, MCL86+, MCL86jr, MCLR5, MCLZ8