highway
riscv-v-spec
| highway | riscv-v-spec | |
|---|---|---|
| 5 | 43 | |
| 1,424 | 858 | |
| -0.1% | - | |
| 0.0 | 6.0 | |
| about 2 years ago | about 2 months ago | |
| JavaScript | Assembly | |
| MIT License | Creative Commons Attribution 4.0 |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
highway
-
Seamless Transition Using Highway.js/Barba.js
It's using Highway.js or Barba.js I am not using any framework on this project.
-
What is e.defaultPrevented and why library authors MUST use it
@dogstudio/highway is one such library that doesn't check for that, and thus preventing the default behavior of an anchor will not prevent further navigation.
-
Which library for page transitions would you advise?
I've come across swup , HighwayJS and barba js
-
Using Three.js with page transitions?
Highway.js is another good replacement for Barba. It's actually built by Dogstudio, so would be exactly what they're using on their site. Yuri also has a tutorial on YouTube for that one.
-
Any Websites that won awwwards for animation/interactivety with open source code?
3 June 2021 - steventaylor.com - this is a Wordpress site whose landing page seems to be mostly an intro video. Additional animation handled by GSAP and Highway.js. These and WP are all open source.
riscv-v-spec
-
Scaleway launches RISC-V servers
Here are some resources I can recommend:
RVV spec (also look at the examples in the repo): https://github.com/riscv/riscv-v-spec/blob/master/v-spec.ado...
RVV intrinsics viewer: https://dzaima.github.io/intrinsics-viewer
Tutorial: RISC-V Vector Extension Demystified (3 hour video going over every instruction): https://youtu.be/oTaOd8qr53U
RISC-V Vector extension in a nutshell: https://fprox.substack.com/p/risc-v-vector-extension-in-a-nu...
If you want to see a more complex example/real world application, then you might also be ibterested ib my article about vectorizing unicode conversions: https://camel-cdr.github.io/rvv-bench-results/articles/vecto...
In terms of development I'd recommend using qemu and a cross compiler, or if you want hardware try to get the kendryte k230 (currently the only sbc with rvv 1.0 support) or wait a bit for better hardware (BPI-F3 and sg2380 should release this year).
- Cray-1 performance vs. modern CPUs
-
x86 vs ARM; Vector and Matrix Extensions; How do they compare?
And this isn't just some theoretical or something unlikely to happen - the official spec already contains such a bug. If the writers of the spec can't get things right, even with the small amount of code in the spec, I don't have high hopes that less informed programmers will. RVV being absurdly complicated (IMO, compared to SVE2 and AVX10) doesn't help its cause here.
- riscv64 is now an official Debian architecture (rebootstrap in progress)
- Vector vs SIMD
-
LLVM's libc Gets Much Faster memcpy For RISC-V
Will the reference one actually be the most optimal one on future hardware?
- Is there any good place to find a copy-paste-able quick reference on RISC-V extensions? Particularly for the vector extension
-
Building a toolchain suitable for compiling V extension code
I'll do a deep dive into the https://gms.tf/riscv-vector.html#getting-started tutorial, and probably pop the proverbial stack and just study RVV 0.7.1 on its own (using https://github.com/riscv/riscv-v-spec/releases/tag/0.7.1).
-
A weird idea for using RV32E on a RV32I core - multithreaded microcontrollers?
I see your point. You can file a request for it at https://github.com/riscv/riscv-v-spec/issues if you want to pitch it to the relevant ISA bodies. The bar for implementing it pretty high.
-
Examining the Top Five Fallacies About RISC-V
It's not "unusual"; using data registers for mask is a valid tradeoff especially for low-end implementations, whereas higher-end architectures can easily use shadow registers. Discussed in depth at https://github.com/riscv/riscv-v-spec/issues/811
What are some alternatives?
swup - Versatile and extensible page transition library for server-rendered websites 🎉
riscv-p-spec - RISC-V Packed SIMD Extension
Vc - SIMD Vector Classes for C++
highway - Performance-portable, length-agnostic SIMD with runtime dispatch
GreenSock-JS - GSAP (GreenSock Animation Platform), a JavaScript animation library for the modern web
riscv-bitmanip - Working draft of the proposed RISC-V Bitmanipulation extension
oneDNN - oneAPI Deep Neural Network Library (oneDNN)
vroom - VRoom! RISC-V CPU
DirectXMath - DirectXMath is an all inline SIMD C++ linear algebra library for use in games and graphics apps
learn-fpga - Learning FPGA, yosys, nextpnr, and RISC-V
nsimd - Agenium Scale vectorization library for CPUs and GPUs
meetings - WebAssembly meetings (VC or in-person), agendas, and notes