ARM7
Implemetation of pipelined ARM7TDMI processor in Verilog (by chsasank)
ARM-LEGv8
Verilog Implementation of an ARM LEGv8 CPU (by nxbyte)
| ARM7 | ARM-LEGv8 | |
|---|---|---|
| 1 | 1 | |
| 73 | 85 | |
| - | - | |
| 10.0 | 10.0 | |
| about 6 years ago | over 5 years ago | |
| Verilog | Verilog | |
| MIT License | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
ARM7
Posts with mentions or reviews of ARM7.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-11-09.
ARM-LEGv8
Posts with mentions or reviews of ARM-LEGv8.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-11-09.
What are some alternatives?
When comparing ARM7 and ARM-LEGv8 you can also consider the following projects:
ARM_Cortex-M3 - 该项目依据全国大学生集成电路创新创业大赛“ARM杯”赛题要求，在FPGA上搭建Cortex-M3软核、图像协处理器，并通过OV5640摄像头采集车牌图像，实现对车牌的识别与结果显示。项目基于Altera DE1 FPGA搭载Cortex-M3软核，依据AHB-Lite总线协议，将LCD1602、RAM、图像协处理器等外设挂载至Cortex-M3。视频采集端，设计写FiFo模块、SDRAM存储与输出、读FiFo模块、灰度处理模块、二值化、VGA显示等模块。最终将400位宽的结果数据（对应20张车牌）存储在RAM中，输出至AHB总线，由Cortex-M3调用并显示识别结果。 [UnavailableForLegalReasons - Repository access blocked]
ARM9-compatible-soft-CPU-core - This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.