8-bit-CPU VS iverilog

I later built a version that can read/store a full byte (2 key-presses) and present it to a CPU.

My code is available here, it has evolved since then and I actually abandoned the in-Arduino emulator later (re-wrote that part in Verilog). So it is best viewed at historical tag "emulator_1.0" in the repository.

Mark your data using PROGMEM directive (see example).

My project sources are on GitHub. Theres a lot going on, and it is probably a bit over-engineered. You can start by taking a look at Arduino sketch and client library.

I wrote an emulator for mine, then extended it to test out different designs, before building on hardware. The approach was a bit different, as I started by implementing 74-series logic chips. Then "wired" them together into CPU modules. This way emulator becomes a testable representation of what's possible using logic chips.

I wrote an emulator for my CPU in Verilog. Actually, I made it to test out various aspects before building, real hardware has not yet cached up with it.

The source code was in Python. I was able to debug it using Arduino-based adapter and (by using some "magic") translate into machine code binary. Since then I've switched to CustomAsm for code compilation and have other means to debug (emulator and debugger tool).

If you looking for examples: here's how you create the array (code generated using xxd -i command), and here's how you use the array.

In the beginning of program (on EEPROM), there's a small piece of code that reads all 256 address locations and writes them back. In BOOT mode, this effectively copies contents from ROM into RAM.

Complicated? Perhaps, but do not underestimate the power of automated testing! When you can run a couple dozen tests in just few seconds, at any time, it really gives you confidence about the system. Obviously, one should spend time writing the tests, but it pays back rather quickly.

Also, Icarus says that they do not support assertions in their full-generality either:

The toolchains come with their own simulators, but there are also open source ones you can use. For Verilog you have ICARUS Verilog and Verilator. For VHDL there is GHDL.

This is not, in general, true. While iverilog may support some SV features, it is far from complete and does not support some very common use cases. For example, interfaces.

However, I find that it's always read-before-write in Icarus Verilog. Is my tool wrong? Is the book wrong? Is this situation actually ambiguous?

I have no intention to run it on real FPGA ever, Icarus Verilog simulator suits me well enough.

As the idea was to make it more realistic, I started by making (hopefully accurate representation of) 74-series logic chips in Verilog. Then wired them into higher level modules, and merged those into complete CPU. Runs quite good in Icarus Verilog.

I'd suggest starting with simulation using Icarus Verilog or Verilator. And gtkwave to display simulation output.

We'll specifically be using Icarus Verilog.

In the open-source world, learning UVM isn't practical. There just isn't a simulator that can run it. However, if you use something like PyUVM with CocoTB, along with verilator or Icarus as an RTL simulator you code start writing test benches around some simple verilog components.