6502-exp
vhdl-tutorial
| 6502-exp | vhdl-tutorial | |
|---|---|---|
| 1 | 1 | |
| 0 | 67 | |
| - | - | |
| 10.0 | 4.0 | |
| about 3 years ago | 9 months ago | |
| Assembly | VHDL | |
| - | GNU General Public License v3.0 only |
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6502-exp
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Learning Verilog and FPGA
Chisel is compiled to Verilog so it has excellent interoperability. You can use Chisel in an existing Verilog project or use existing Verilog modules in a Chisel project. Therefore it is already supported by practically all vendors and simulators.
I've used Chisel to interface with proprietary Lattice DSPs and RAM modules, and I'm sure you could do the same with other vendors as well. All you have to do is define the IOs and parameters of the module. In Chisel this is called a "Blackbox". Example: https://github.com/fayalalebrun/6502-exp/blob/master/src/mai...
vhdl-tutorial
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Learning Verilog and FPGA
Greg Stitt shares amazing training materials freely (he uses them for his undergraduate and graduate courses). His synthesizable HDL methods are really empowering for beginner developers
https://github.com/ARC-Lab-UF/vhdl-tutorial
http://www.gstitt.ece.ufl.edu/
What are some alternatives?
apio - :seedling: Open source ecosystem for open FPGA boards
prince - The Prince lightweight block cipher in Verilog.
icestorm - Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
prjtrellis - Documenting the Lattice ECP5 bit-stream format.
f4pga-arch-defs - FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.