Pipelined RISC-V RV32I Core in Verilog
Why do you think that https://github.com/maikmerten/spu32 is a good alternative to Toast-RV32i
Pipelined RISC-V RV32I Core in Verilog
Why do you think that https://github.com/maikmerten/spu32 is a good alternative to Toast-RV32i