Vivado-Design-Tutorials

By Xilinx
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  • Versal implementation Vivado 2021.2.1
    1 project | /r/FPGA | 3 May 2022
    I didn't modify anything, and one of these example is just a .tcl to run (https://github.com/Xilinx/Vivado-Design-Tutorials/tree/2021.1/Device_Architecture_Tutorials/Versal/NoC_DDRMC/Performance_Tuning) and the same problem happens. ( I modified the .tcl to match my versions of Vivado/CIPS)

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Xilinx/Vivado-Design-Tutorials is an open source project licensed under MIT License which is an OSI approved license.

The primary programming language of Vivado-Design-Tutorials is Tcl.


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