Versal implementation Vivado 2021.2.1

This page summarizes the projects mentioned and recommended in the original post on /r/FPGA

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  • Vivado-Design-Tutorials

    • I didn't modify anything, and one of these example is just a .tcl to run (https://github.com/Xilinx/Vivado-Design-Tutorials/tree/2021.1/Device_Architecture_Tutorials/Versal/NoC_DDRMC/Performance_Tuning) and the same problem happens. ( I modified the .tcl to match my versions of Vivado/CIPS)

  • InfluxDB

    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

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NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a more popular project.

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