External Quad SPI pins?

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  • The RP2040 differs from most cheap microcontrollers in that it has two CPU cores (they even threw in a programmer friendly hardware interface in the form of a pair of FIFOs (with interrupt support) and hardware spinlocks). Dedicating one of your two CPU cores to hard realtime bitbanging is a simple solution to annoying to interface with protocols, but most of the time PIO is the better solution. Using them as 1 bit wide SPI is among the simplest uses for them. The official example collection contains code doing just that: PIO SPI example code. Extending the example to transfer 4 instead of 1 bits and half duplex instead of full duplex should get you there. The PIO state machines are connected to short FIFOs and best served through DMA for high bandwidth applications. This gets you as many fast QSPI interfaces with low CPU utilisation as there are GPIO pins to map them to.

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