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There's a lot of documentation on my github, both for the processor implementation itself, and also the ISA and assembler. Including a blueprint of the entire processor, if you're interested, although feel free to message me if you have other questions, I'm happy to answer!
(seriously though, maybe you could redo this in a high speed logic simulator like Digital and then throw it on an FPGA hooked up to a Monitor/TV)
I have a RISCV cpu in combinators, but the ISA has many features not well suited for Factorio, so the CPU pulls only ~3.2 ticks per instruction.