Show HN: RISC-V core written in 600 lines of C89

• rv

  4 574 8.4 C

  32-bit RISC-V CPU in ~800 lines of C89

• riscv-disassembler

  1 53 10.0 C

  A minimal RISC-V RV32I disassembler

How about a RISC-V disassembler in 200 lines of C99?

https://github.com/andportnoy/riscv-disassembler/blob/master...

• InfluxDB

  www.influxdata.com sponsored

  Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

  

• edgetpu

  34 397 2.7 C++

  Coral issue tracker (and legacy Edge TPU API source)

  

> even in the 80s I wanted an FPGA accelerators in every machine

Mostly unrelated, but I recently discovered that you can buy TPUs, right now, as a consumer product, from https://coral.ai.

The stock firmware already allows you to run these things so hard they overheat, which is amazing.

But yes, I also want FPGA accelerators.

Suggest a related project