Verilog wishbone-bus

Open-source Verilog projects categorized as wishbone-bus | Edit details

Top 7 Verilog wishbone-bus Projects

  • GitHub repo zipcpu

    A small, light weight, RISC CPU soft core

    Project mention: What modules/hardware would you like to see? | | 2021-05-14

    I've posted quite a few AXI designs on github. These include an AXI Crossbar, an AX DMA, and even an AXI scatter-gather based DMA. Some of my recent postings even include instruction or [data](instruction caches.

  • GitHub repo wb2axip

    Bus bridges and other odds and ends

    Project mention: SoC FPGA design to ASIC | | 2021-07-22

    How about an interconnect? I've posted just about all the necessary components for building one. If you look hard enough, you'll find that others have done so as well.

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  • GitHub repo wbuart32

    A simple, basic, formally verified UART controller

    Project mention: How can I get Verilator to Prompt for User Input? | | 2021-04-19

    The core component to the single simulated to TCP port can be found here, in uartsim.cpp. You can find a companion software program that will forward the same TCP port to a hardware serial port here, under the name netuart.cpp.

  • GitHub repo openarty

    An Open Source configuration of the Arty platform

    Project mention: FPGA and Simulation tools for Risc-V design | | 2020-12-24

    I'd then recommend Verilator for simulation testing--but only after your formal design checking is complete. You can find online C++ models of a QSPI flash, RAM, and a serial port which should be good enough to get you going here. When you are ready for more permanent storage, there's also a decent C++ model of an SD card (SPI only).

  • GitHub repo sdspi

    SD-Card controller, using a SPI interface that is (optionally) shared

    Project mention: SoC FPGA design to ASIC | | 2021-07-22

    How about an SD card controller? I know I have a SPI based SD card controller, but the SDIO isn't that much harder. If you look hard enough you can find open source SDIO controllers.

  • GitHub repo wbscope

    A wishbone controlled scope for FPGA's

    Project mention: Working with FPGAs (Questions) | | 2021-07-10

    One of my first projects on my own was a design that allowed me to interact with a bus from an external UART. I then built my own internal logic analyzer. From these humble beginnings, I fairly well insulated myself from the vendor architectures out there since I can do all of my design in Verilog.

  • GitHub repo dbgbus

    A collection of debugging busses developed and presented at

    Project mention: Need help with Objcopy for Verilog Hex File | | 2021-07-07

    As examples: - Here's how I process libelf to provide me with an array of section pointers, each containing the address to load the values at - Here's where I then load the values into my design when I'm using an external loader via a debugging bus. - Here's another copy of the same, this time running from within Verilator rather than from within externally controlled logic.

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NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2021-07-22.


What are some of the best open-source wishbone-bus projects in Verilog? This list will help you:

Project Stars
1 zipcpu 703
2 wb2axip 210
3 wbuart32 144
4 openarty 85
5 sdspi 54
6 wbscope 53
7 dbgbus 19