Top 3 Verilog system-on-chip Projects
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.Project mention: Resources for a physical design engineer | reddit.com/r/chipdesign | 2021-07-20
Specifically openlane (https://github.com/The-OpenROAD-Project/OpenLane is a great way to start, although it's very painful trying to do complex designs. However, they're pretty helpful answering questions on Gitter
The Antikernel operating system projectProject mention: Check out this state machine reading+writing /dev/stdin and stdout from an FPGA to play a little guessing game at the console. Code in comments. | reddit.com/r/FPGA | 2021-07-14
Scout APM: A developer's best friend. Try free for 14-days. Scout APM uses tracing logic that ties bottlenecks to source code so you know the exact line of code causing performance issues and can get back to building a great product faster.
A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systemsProject mention: How do you successfully compile a working verilator package on Ubuntu? | reddit.com/r/ZipCPU | 2021-07-27
Let me also point out that I rarely use Verilators -exe flag. I tend instead to build my designs in steps: 1) Run Verilator, 2) run make -f Vtoplvl.mk in the obj_dir directory, 3) turn my test script into an object file, and only then 4) link everything together into an executable. I've also been known for peeking at Verilator's internal variables during a simulation run--but that may be another topic entirely.