Verilog system-on-chip

Open-source Verilog projects categorized as system-on-chip | Edit details

Top 3 Verilog system-on-chip Projects

  • GitHub repo openlane

    OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

    Project mention: Resources for a physical design engineer | | 2021-07-20

    Specifically openlane ( is a great way to start, although it's very painful trying to do complex designs. However, they're pretty helpful answering questions on Gitter

  • GitHub repo antikernel

    The Antikernel operating system project

    Project mention: Check out this state machine reading+writing /dev/stdin and stdout from an FPGA to play a little guessing game at the console. Code in comments. | | 2021-07-14
  • Scout APM

    Scout APM: A developer's best friend. Try free for 14-days. Scout APM uses tracing logic that ties bottlenecks to source code so you know the exact line of code causing performance issues and can get back to building a great product faster.

  • GitHub repo zbasic

    A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems

    Project mention: How do you successfully compile a working verilator package on Ubuntu? | | 2021-07-27

    Let me also point out that I rarely use Verilators -exe flag. I tend instead to build my designs in steps: 1) Run Verilator, 2) run make -f in the obj_dir directory, 3) turn my test script into an object file, and only then 4) link everything together into an executable. I've also been known for peeking at Verilator's internal variables during a simulation run--but that may be another topic entirely.

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2021-07-27.


What are some of the best open-source system-on-chip projects in Verilog? This list will help you:

Project Stars
1 openlane 375
2 antikernel 95
3 zbasic 29