Verilog Cpu

Open-source Verilog projects categorized as Cpu | Edit details

Top 3 Verilog Cpu Projects

  • GitHub repo darkriscv

    opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

    Project mention: Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux | reddit.com/r/linux | 2021-06-26

    Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.

  • GitHub repo zipcpu

    A small, light weight, RISC CPU soft core

    Project mention: What modules/hardware would you like to see? | reddit.com/r/FPGA | 2021-05-14

    I've posted quite a few AXI designs on github. These include an AXI Crossbar, an AX DMA, and even an AXI scatter-gather based DMA. Some of my recent postings even include instruction or [data](instruction caches.

  • GitHub repo biriscv

    32-bit Superscalar RISC-V CPU

    Project mention: BiRISC-V – 32-bit Superscalar RISC-V CPU | news.ycombinator.com | 2021-07-20
NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2021-07-20.

Index

What are some of the best open-source Cpu projects in Verilog? This list will help you:

Project Stars
1 darkriscv 1,149
2 zipcpu 698
3 biriscv 273