Top 3 Verilog Cpu Projects
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!Project mention: Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux | reddit.com/r/linux | 2021-06-26
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.
A small, light weight, RISC CPU soft coreProject mention: What modules/hardware would you like to see? | reddit.com/r/FPGA | 2021-05-14
I've posted quite a few AXI designs on github. These include an AXI Crossbar, an AX DMA, and even an AXI scatter-gather based DMA. Some of my recent postings even include instruction or [data](instruction caches.
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32-bit Superscalar RISC-V CPUProject mention: BiRISC-V – 32-bit Superscalar RISC-V CPU | news.ycombinator.com | 2021-07-20