Standard ML Verilog Projects
Verilog development and verification project for HOL4 (by CakeML)Project mention: Lutsig - A verified Verilog synthesizer | reddit.com/r/FPGA | 2021-01-11
All source code and proofs are available on Github: https://github.com/CakeML/hardware. However, if you are not familiar with the HOL4 theorem prover it's not entirely straightforward to run Lutsig since you currently have to run Lutsig inside the theorem prover.
Are you hiring? Post a new remote job listing for free.