Standard ML Verilog

Open-source Standard ML projects categorized as Verilog | Edit details

Standard ML Verilog Projects

  • GitHub repo hardware

    Verilog development and verification project for HOL4 (by CakeML)

    Project mention: Lutsig - A verified Verilog synthesizer | reddit.com/r/FPGA | 2021-01-11

    All source code and proofs are available on Github: https://github.com/CakeML/hardware. However, if you are not familiar with the HOL4 theorem prover it's not entirely straightforward to run Lutsig since you currently have to run Lutsig inside the theorem prover.

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2021-01-11.

Index

Project Stars
1 hardware 10
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