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Stars | Project | Description |
|---|---|---|---|
| 1 | 45 | The BERI and CHERI processor and hardware platform | |
| 1 | 16 | RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT | |
| 1 | 10 | RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance | |
| 2 | 7 | A high-throughput, parameterized, parallel crc hardware implementation. |
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