wasm-lisp VS riscv-v-spec

It is a lot, but not quite 1000, yet. From https://webassembly.github.io/spec/core/appendix/index-instr... I see 436 instructions including SIMD which is over half the population. If I filtered it correctly, it looks like there are about 203 instructions in Wasm without SIMD. Many of those are not necessary for most programs.

There at least three small Wasm interpreters in Rust

4kloc https://github.com/yblein/rust-wasm

3kloc https://github.com/k-nasa/wai

500loc https://github.com/rustwasm/wasm-bindgen/tree/HEAD/crates/wa...

This list has 169 Wasm instructions https://github.com/rolfrm/wasm-lisp/blob/master/instruction....

Wirth's RISC is neat, I'd love to re-do it in RISC-V (only 47 instructions in the base ISA). UM, Chifir and UXN look like Art (not pejorative), I'll definitely read the Chifir paper. They would be great systems to run on top of Wasm.

https://git.sr.ht/~bctnry/chifir

One might be able squeeze a Chifir VM into an ESP-32 (with external PSRAM).

Here are some resources I can recommend:

RVV spec (also look at the examples in the repo): https://github.com/riscv/riscv-v-spec/blob/master/v-spec.ado...

RVV intrinsics viewer: https://dzaima.github.io/intrinsics-viewer

Tutorial: RISC-V Vector Extension Demystified (3 hour video going over every instruction): https://youtu.be/oTaOd8qr53U

RISC-V Vector extension in a nutshell: https://fprox.substack.com/p/risc-v-vector-extension-in-a-nu...

If you want to see a more complex example/real world application, then you might also be ibterested ib my article about vectorizing unicode conversions: https://camel-cdr.github.io/rvv-bench-results/articles/vecto...

In terms of development I'd recommend using qemu and a cross compiler, or if you want hardware try to get the kendryte k230 (currently the only sbc with rvv 1.0 support) or wait a bit for better hardware (BPI-F3 and sg2380 should release this year).

And this isn't just some theoretical or something unlikely to happen - the official spec already contains such a bug. If the writers of the spec can't get things right, even with the small amount of code in the spec, I don't have high hopes that less informed programmers will. RVV being absurdly complicated (IMO, compared to SVE2 and AVX10) doesn't help its cause here.

Will the reference one actually be the most optimal one on future hardware?

I'll do a deep dive into the https://gms.tf/riscv-vector.html#getting-started tutorial, and probably pop the proverbial stack and just study RVV 0.7.1 on its own (using https://github.com/riscv/riscv-v-spec/releases/tag/0.7.1).

I see your point. You can file a request for it at https://github.com/riscv/riscv-v-spec/issues if you want to pitch it to the relevant ISA bodies. The bar for implementing it pretty high.

It's not "unusual"; using data registers for mask is a valid tradeoff especially for low-end implementations, whereas higher-end architectures can easily use shadow registers. Discussed in depth at https://github.com/riscv/riscv-v-spec/issues/811