subleq VS swapforth

Compare subleq vs swapforth and see what are their differences.


16-bit SUBLEQ CPU running eForth - just for fun (by howerj)


Swapforth is a cross-platform ANS Forth (by jamesbowman)
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subleq swapforth
8 4
39 251
- -
3.5 0.0
about 24 hours ago 5 months ago
Forth Forth
The Unlicense BSD 3-clause "New" or "Revised" License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
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Posts with mentions or reviews of subleq. We have used some of these posts to build our list of alternatives and similar projects.

We haven't tracked posts mentioning subleq yet.
Tracking mentions began in Dec 2020.


Posts with mentions or reviews of swapforth. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-11-25.
  • FPGAs for interpreted programming languages?
    2 projects | | 25 Nov 2022
  • How many LUT for an 8 bit CPU?
    2 projects | | 11 Nov 2022
    Thanks! Found the port of this to the board I want :)
  • The RISC Deprogrammer
    2 projects | | 28 Oct 2022
    It's a standard thing to do in EE curricula; you normally do it in a one-semester class, and there are literally thousands of open-source synthesizable CPU cores on GitHub now.

    To take two examples to show that designing a CPU is less work than writing a novel:

    - Chuck Thacker's "A Tiny Computer", fairly similar to the Nova, is a page and a half of synthesizable Verilog; it runs at 66 MHz in 200 LUTs of a Virtex-5:

    - James Bowman's J1A is more like Chuck Moore's MuP21 and is about three pages of synthesizable Verilog: and You can build it with Claire Wolf's iCEStorm (yosys, etc.) and run it on any but Lattice's tiniest FPGAs; it takes up 1162 4-input LUTs.

    I haven't quite done it myself. Last time I played it took me a couple of hours to play through the hardware design levels. But that's not really "design" in the sense of defining the instruction set (which is also kind of Nova-like), thinking through state machine design, and trying different pipeline depths; you're mostly just doing the kind of logic minimization exercises you'd normally delegate to yosys.

    In I designed a CPU instruction set, wrote a simulator for it, wrote and tested some simple programs, designed a CPU at the RTL level, and sketched out gate-level logic designs to get an estimate of how big it would be. But I haven't simulated the RTL to verify it, written it down in an HDL, or breadboarded the circuit, so I'm reluctant to say that this qualifies as "designing a single CPU" either.

What are some alternatives?

When comparing subleq and swapforth you can also consider the following projects:

arkam - A Simple Stack VM and Forth

gforth - Gforth mirror on GitHub (original is on Savannah)

Mako - A simple virtual game console

durexforth - Modern C64 Forth

lbForth - Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.

elfort - A Forth metacompiler that directly emits an executable binary for x86-64 Linux written in Arkam

gforth-raylib - Raylib 3.5 bindings for Gforth. The name is backwards for obvious reasons.