solo-forth VS swapforth

I can only compare it with Abersoft Forth on ZX Spectrum. While I admire the Forth implementation in Jupiter Ace a lot, it lacks a lot of basic words. Users can often find them implemented in the manual, but they are not immediately available. 8kB ROM is really on the edge of usability. Jupiter Ace Forth uses an unusual approach to code editing based on decompilation instead of screens, which is closer to how Basic worked. Abersoft Forth was much faster and had better graphics support.

The modern Solo Forth is worth mentioning too: https://github.com/programandala-net/solo-forth?tab=readme-o...

Thanks! Found the port of this to the board I want :) https://github.com/jamesbowman/swapforth/tree/master/j1a

It's a standard thing to do in EE curricula; you normally do it in a one-semester class, and there are literally thousands of open-source synthesizable CPU cores on GitHub now.

To take two examples to show that designing a CPU is less work than writing a novel:

- Chuck Thacker's "A Tiny Computer", fairly similar to the Nova, is a page and a half of synthesizable Verilog; it runs at 66 MHz in 200 LUTs of a Virtex-5: https://www.cl.cam.ac.uk/~swm11/examples/bluespec/Tiny3/Thac...

- James Bowman's J1A is more like Chuck Moore's MuP21 and is about three pages of synthesizable Verilog: https://github.com/jamesbowman/swapforth/blob/master/j1a/ver... and https://github.com/jamesbowman/swapforth/blob/master/j1a/ver.... You can build it with Claire Wolf's iCEStorm (yosys, etc.) and run it on any but Lattice's tiniest FPGAs; it takes up 1162 4-input LUTs.

I haven't quite done it myself. Last time I played https://nandgame.com/ it took me a couple of hours to play through the hardware design levels. But that's not really "design" in the sense of defining the instruction set (which is also kind of Nova-like), thinking through state machine design, and trying different pipeline depths; you're mostly just doing the kind of logic minimization exercises you'd normally delegate to yosys.

In https://github.com/kragen/calculusvaporis I designed a CPU instruction set, wrote a simulator for it, wrote and tested some simple programs, designed a CPU at the RTL level, and sketched out gate-level logic designs to get an estimate of how big it would be. But I haven't simulated the RTL to verify it, written it down in an HDL, or breadboarded the circuit, so I'm reluctant to say that this qualifies as "designing a single CPU" either.

Also worth checking is the Swapforth Github repository.