Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
safeclib
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LLVM's Libc Gets Much Faster memcpy For RISC-V
Of course assembler spezializations are an anti-pattern, because the optimizer should be fixed to do it much better. Better C code is often 2x faster than hand optimized assembler.
Eg my C memcpy with inlined and vectorized clang beats glibc or gcc memcpy in assembler easily. https://github.com/rurban/safeclib/blob/master/tests/perf_me...
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Site with common coding mistakes that cause security threats with code examples?
+1 This along with https://github.com/rurban/safeclib (and its forks/derivatives).
- Safeclib – C11 Annex K implementation
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What are the major dialects of C nowadays?
I have yet to look into Annex K. It didn't seem to gain much traction. Some people at Red Hat wrote a field experience report about it. I recently discovered an implementation of Annex K functions that claims to be pretty portable, safeclib.
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memmove_s?
See my testsuite and remarks at https://github.com/rurban/safeclib/blob/master/doc/libc-overview.md , esp. towards the windows implementation
- Why does Windows 10 run faster than Fedora?
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A 100LOC C impl of memset, that is faster than glibc's
I do it because nobody else implemented a secure memset. What they call secure is just avoiding that the compiler ignores it. A secure memset also cleans the caches with a memory barrier, so that meltdown cannot read it.
explicit_bzero and it's numerous variants are not only insecure, but also slow. (byte wise!)
Only safelibc has a secure memset_s. https://github.com/rurban/safeclib/blob/master/tests/perf_me...
qemu
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QEMU AioContext removal and how it was done
https://gitlab.com/qemu-project/qemu/-/blob/master/hw/scsi/s...
QEMU's IOThreads allow the user to configure the threads and get something similar to thread per core architecture. But if 1 thread becomes a bottleneck, then some form of thread synchronization is needed again even with thread per core architecture. Some problems can be parallelized and they work well with thread per core.
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Why are Apple Silicon VMs so different?
Add `ENV ERL_FLAGS="+JPperf true"` to your Dockerfile and it will build just fine cross platform. The flag just changes some things during build time and won’t affect runtime performance.
[1] https://gitlab.com/qemu-project/qemu/-/issues/1034
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RISC-V Vector benchmark results
> I don't know how rdcycle works on qemu.
That's a good question! I had to look it up myself ...
Obviously qemu TCG isn't a cycle-accurate emulation. Using RDCYCLE / reading the corresponding CSR eventually calls https://gitlab.com/qemu-project/qemu/-/blob/69680740eafa1838... which calls cpu_get_host_ticks is basically an arch-independent wrapper around RDTSC.
So it just measures the time taken to run using RDTSC. Which I guess is what you would want (maybe?). It would measure the time taken to emulate the vector instruction in host instructions.
> This benchmark is more meant for developers to figure out how to vectorize algorithms effectively, as in which instructions to choose.
Absolutely, I'm not saying the qemu results would say anything very deep, but they're kind of interesting from the point of view of either optimizing qemu or if you have to use qemu because the hardware you want isn't available / isn't cheap enough.
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The IMPOSSIBLE RISCV HACK: Vector Extension 0.7.1-draft w/ current Linux kernel! – René Rebe
I see the commits that started switch support from RVV 071 to 100 start here, https://gitlab.com/qemu-project/qemu/-/commit/9ec6622db30df1c00d863c1ffc33341f9e0a534d
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I booted Linux 292,612 times
>> https://gitlab.com/qemu-project/qemu/-/issues/1696 ]
> Can I please just get the detail in mail instead of having to go look at random websites?
Maybe it's me but if I did boot boot linux 292.612 times to find a bug, you might as well click a link to a repository of a major open source project on a major git hosting service.
Is it really that weird to ask people online to check a website? Maybe I don't know the etiquette of these mail lists so this is a geniune question.
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Rise: Accelerate the Development of Open Source Software for RISC-V
Capstone is used[1] by QEMU as disassembly engine in debug logs and in monitor mode debugger, by the way, so it's in the scope of the RISE effort.
[1] https://gitlab.com/qemu-project/qemu/-/blob/master/disas/cap...
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Intel Arc 750 Crashes Host + Display Cable Workaround not needed anymore (Windows)
A user on the qemu bugtracker found a way to get the Intel Arc working across resets without crashing the host: Just don't passthrough the audio device of the GPU and everything works!
- Qemu 7.2.2: command line syntax in libvirt domain changed
- Anyone know if there's a way to disable ReBar on only one GPU?
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[RFT] Allow QEMU to expose static REBAR capability
[1]https://gitlab.com/qemu-project/qemu/-/commit/3412d8ec9810b819f8b79e8e0c6b87217c876e32 [2]https://gitlab.com/alex.williamson/qemu/-/commit/9a6d1822a2bd55f5dee1aec1b6529ae57949d5ba.patch
What are some alternatives?
memset_benchmark - This repository contains high-performance implementations of memset and memcpy in assembly.
gcc
riscv-binutils-gdb - RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
libu8ident - unicode security guidelines for identifiers
nbdkit
fancy-memset - small, fast memset based on microsoft's design
lzbench - lzbench is an in-memory benchmark of open-source LZ77/LZSS/LZMA compressors
copies-and-fills
CLK - A latency-hating emulator of: the Acorn Electron and Archimedes, Amstrad CPC, Apple II/II+/IIe and early Macintosh, Atari 2600 and ST, ColecoVision, Enterprise 64/128, Commodore Vic-20 and Amiga, MSX 1/2, Oric 1/Atmos, early PC compatibles, Sega Master System, Sinclair ZX80/81 and ZX Spectrum.
fancy-memcmp - small, fast memcmp
riscv-gnu-toolchain - GNU toolchain for RISC-V, including GCC