rvv_example
Simple demonstration of using the RISC-V Vector extension (by brucehoult)
rvv-intrinsic-doc
By riscv-non-isa
rvv_example | rvv-intrinsic-doc | |
---|---|---|
2 | 6 | |
29 | 254 | |
- | 2.4% | |
3.1 | 8.6 | |
15 days ago | 8 days ago | |
Assembly | C | |
- | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
rvv_example
Posts with mentions or reviews of rvv_example.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-09-12.
rvv-intrinsic-doc
Posts with mentions or reviews of rvv-intrinsic-doc.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-09-12.
- Fixed length attributes · Issue #176 · riscv-non-isa/rvv-intrinsic-doc
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GCC 13.1 is now out... adds RVV vector intrinsics
Support for vector intrinsics as specified in version 0.11 of the RISC-V vector intrinsic specification, thanks Ju-Zhe Zhong from RiVAI for contributing most of implementation.
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RVV 1.0 assembly language example
The docs at https://github.com/riscv-non-isa/rvv-intrinsic-doc makes me think there should be a vfmacc_vv_f32m1_ta. I'll raise an issue there if it really is missing and not just me misunderstanding / using outdated stuff.
- Compiler Explorer supports RISC-V Clang with vector intrinsics
- Porting an AVX-512 neural net C99 code generator to RISC-V
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SQL on RISC-V Chip in Rust
If you're doing physics modeling or calculating light refractions or other stuff where you, a highly trained professional, have profiled and know that you'd benefit from V and the optimizer just isn't doing it, you can meet in the middle. The Vector Intrinsics are the contract between that highly trained professional and the compiler that aren't quite programming in assembly and handle the absurd avalanche (made easy by templates, but hard by C) of a templated/body that the optimizer can then easily inline without calling overhead and without blowing register allocation. It handles things like the generation of the 176 ways to find a maximum integer in an array. This is kind of the compromise between the autovectorization code not being able to decompose your nested Fortran loops or lighting effect in graphics or whatever but not quite reaching despair and coding it in assembly yourself. If you've ever programmed MMX, this will all look familiar.
What are some alternatives?
When comparing rvv_example and rvv-intrinsic-doc you can also consider the following projects:
riscv-v-spec - Working draft of the proposed RISC-V V vector extension
riscv-isa-sim - Spike, a RISC-V ISA Simulator