rvv_example
riscv-v-spec
| rvv_example | riscv-v-spec | |
|---|---|---|
| 2 | 43 | |
| 29 | 858 | |
| - | - | |
| 3.1 | 6.0 | |
| 15 days ago | about 2 months ago | |
| Assembly | Assembly | |
| - | Creative Commons Attribution 4.0 |
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rvv_example
riscv-v-spec
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Scaleway launches RISC-V servers
Here are some resources I can recommend:
RVV spec (also look at the examples in the repo): https://github.com/riscv/riscv-v-spec/blob/master/v-spec.ado...
RVV intrinsics viewer: https://dzaima.github.io/intrinsics-viewer
Tutorial: RISC-V Vector Extension Demystified (3 hour video going over every instruction): https://youtu.be/oTaOd8qr53U
RISC-V Vector extension in a nutshell: https://fprox.substack.com/p/risc-v-vector-extension-in-a-nu...
If you want to see a more complex example/real world application, then you might also be ibterested ib my article about vectorizing unicode conversions: https://camel-cdr.github.io/rvv-bench-results/articles/vecto...
In terms of development I'd recommend using qemu and a cross compiler, or if you want hardware try to get the kendryte k230 (currently the only sbc with rvv 1.0 support) or wait a bit for better hardware (BPI-F3 and sg2380 should release this year).
- Cray-1 performance vs. modern CPUs
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x86 vs ARM; Vector and Matrix Extensions; How do they compare?
And this isn't just some theoretical or something unlikely to happen - the official spec already contains such a bug. If the writers of the spec can't get things right, even with the small amount of code in the spec, I don't have high hopes that less informed programmers will. RVV being absurdly complicated (IMO, compared to SVE2 and AVX10) doesn't help its cause here.
- riscv64 is now an official Debian architecture (rebootstrap in progress)
- Vector vs SIMD
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LLVM's libc Gets Much Faster memcpy For RISC-V
Will the reference one actually be the most optimal one on future hardware?
- Is there any good place to find a copy-paste-able quick reference on RISC-V extensions? Particularly for the vector extension
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Building a toolchain suitable for compiling V extension code
I'll do a deep dive into the https://gms.tf/riscv-vector.html#getting-started tutorial, and probably pop the proverbial stack and just study RVV 0.7.1 on its own (using https://github.com/riscv/riscv-v-spec/releases/tag/0.7.1).
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A weird idea for using RV32E on a RV32I core - multithreaded microcontrollers?
I see your point. You can file a request for it at https://github.com/riscv/riscv-v-spec/issues if you want to pitch it to the relevant ISA bodies. The bar for implementing it pretty high.
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Examining the Top Five Fallacies About RISC-V
It's not "unusual"; using data registers for mask is a valid tradeoff especially for low-end implementations, whereas higher-end architectures can easily use shadow registers. Discussed in depth at https://github.com/riscv/riscv-v-spec/issues/811
What are some alternatives?
rvv-intrinsic-doc
riscv-p-spec - RISC-V Packed SIMD Extension
highway - Performance-portable, length-agnostic SIMD with runtime dispatch
highway - Highway - A Modern Javascript Transitions Manager
riscv-bitmanip - Working draft of the proposed RISC-V Bitmanipulation extension
vroom - VRoom! RISC-V CPU
learn-fpga - Learning FPGA, yosys, nextpnr, and RISC-V
meetings - WebAssembly meetings (VC or in-person), agendas, and notes
rvv-encoder - RISC-V V Extension Encoder
riscv-gnu-toolchain - GNU toolchain for RISC-V, including GCC
riscv-isa-manual - RISC-V Instruction Set Manual
riscv-crypto - RISC-V cryptography extensions standardisation work.