riscv-v-spec
sectorlisp
riscv-v-spec | sectorlisp | |
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43 | 25 | |
858 | 1,175 | |
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6.0 | 4.3 | |
about 2 months ago | 5 months ago | |
Assembly | C | |
Creative Commons Attribution 4.0 | ISC License |
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riscv-v-spec
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Scaleway launches RISC-V servers
Here are some resources I can recommend:
RVV spec (also look at the examples in the repo): https://github.com/riscv/riscv-v-spec/blob/master/v-spec.ado...
RVV intrinsics viewer: https://dzaima.github.io/intrinsics-viewer
Tutorial: RISC-V Vector Extension Demystified (3 hour video going over every instruction): https://youtu.be/oTaOd8qr53U
RISC-V Vector extension in a nutshell: https://fprox.substack.com/p/risc-v-vector-extension-in-a-nu...
If you want to see a more complex example/real world application, then you might also be ibterested ib my article about vectorizing unicode conversions: https://camel-cdr.github.io/rvv-bench-results/articles/vecto...
In terms of development I'd recommend using qemu and a cross compiler, or if you want hardware try to get the kendryte k230 (currently the only sbc with rvv 1.0 support) or wait a bit for better hardware (BPI-F3 and sg2380 should release this year).
- Cray-1 performance vs. modern CPUs
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x86 vs ARM; Vector and Matrix Extensions; How do they compare?
And this isn't just some theoretical or something unlikely to happen - the official spec already contains such a bug. If the writers of the spec can't get things right, even with the small amount of code in the spec, I don't have high hopes that less informed programmers will. RVV being absurdly complicated (IMO, compared to SVE2 and AVX10) doesn't help its cause here.
- riscv64 is now an official Debian architecture (rebootstrap in progress)
- Vector vs SIMD
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LLVM's libc Gets Much Faster memcpy For RISC-V
Will the reference one actually be the most optimal one on future hardware?
- Is there any good place to find a copy-paste-able quick reference on RISC-V extensions? Particularly for the vector extension
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Building a toolchain suitable for compiling V extension code
I'll do a deep dive into the https://gms.tf/riscv-vector.html#getting-started tutorial, and probably pop the proverbial stack and just study RVV 0.7.1 on its own (using https://github.com/riscv/riscv-v-spec/releases/tag/0.7.1).
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A weird idea for using RV32E on a RV32I core - multithreaded microcontrollers?
I see your point. You can file a request for it at https://github.com/riscv/riscv-v-spec/issues if you want to pitch it to the relevant ISA bodies. The bar for implementing it pretty high.
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Examining the Top Five Fallacies About RISC-V
It's not "unusual"; using data registers for mask is a valid tradeoff especially for low-end implementations, whereas higher-end architectures can easily use shadow registers. Discussed in depth at https://github.com/riscv/riscv-v-spec/issues/811
sectorlisp
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are there any benchmarks on sector lisp
I'm assuming you are referring to https://github.com/jart/sectorlisp which I gather is an attempt to make a Lisp that fits in a disk boot sector?
- Sectorlisp
- Kilo Lisp: A Kilo Byte-Sized Lisp System
- For the LISP 1.5 mainframe fans here...
- Ask HN: Best book to learn C in 2022?
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Take More Screenshots
I think SIMD was a distraction to our conversation, most code doesn't use it and in the future the length agnostic, flexible vectors; https://github.com/WebAssembly/flexible-vectors/blob/master/... are a better solution. They are a lot like RVV; https://github.com/riscv/riscv-v-spec, research around vector processing is why RISC-V exists in the first place!
I was trying to find the smallest Rust Wasm interpreters I could find, I should have read the source first, I only really use wasmtime, but this one looks very interesting, zero deps, zero unsafe.
16.5kloc of Rust https://github.com/rhysd/wain
The most complete wasm env for small devices is wasm3
20kloc of C https://github.com/wasm3/wasm3
I get what you are saying as to be so small that there isn't a place of bugs to hide.
> “There are two ways of constructing a software design: One way is to make it so simple that there are obviously no deficiencies, and the other way is to make it so complicated that there are no obvious deficiencies. The first method is far more difficult.” CAR Hoare
Even a 100 line program can't be guaranteed to be free of bugs. These programs need embedded tests to ensure that the layer below them is functioning as intended. They cannot and should not run open loop. Speaking of 300+ reimplementations, I am sure that RISC-V has already exceeded that. The smallest readable implementation is like 200 lines of code; https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/...
I don't think Wasm suffers from the base extension issue you bring up. It will get larger, but 1.0 has the right algebraic properties to be useful forever. Wasm does require an environment, for archival purposes that environment should be written in Wasm, with api for instantiating more envs passed into the first env. There are two solutions to the Wasm generating and calling Wasm problem. First would be a trampoline, where one returns Wasm from the first Wasm program which is then re-instantiated by the outer env. The other would be to pass in the api to create new Wasm envs over existing memory buffers.
See, https://copy.sh/v86/
MS-DOS, NES or C64 are useful for archival purposes because they are dead, frozen in time along with a large corpus of software. But there is a ton of complexity in implementing those systems with enough fidelity to run software.
Lua, Typed Assembly; https://en.wikipedia.org/wiki/Typed_assembly_language and Sector Lisp; https://github.com/jart/sectorlisp seem to have the right minimalism and compactness for archival purposes. Maybe it is sectorlisp+rv32+wasm.
If there are directions you would like Wasm to go, I really recommend attending the Wasm CG meetings.
https://github.com/WebAssembly/meetings
When it comes to an archival system, I'd like it to be able to run anything from an era, not just specially crafted binaries. I think Wasm meets that goal.
https://gist.github.com/dabeaz/7d8838b54dba5006c58a40fc28da9...
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*Laughs in autocmd*
Based on this, the next thing you wrote, and your reference to running a minimal Gentoo: I think you might be a Scheme fan in the making. Scheme is the minimal Lisp. (Okay, that might be sectorlisp which fits in 512 bytes.) It’s hands down my favorite language. While it’s evolved on its own to be more of a superset of Scheme, Racket is my Scheme of choice.
- Bootstrapping Lisp in a Boot Sector
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That's pretty much it!
sectorlisp
What are some alternatives?
riscv-p-spec - RISC-V Packed SIMD Extension
sectorforth - sectorforth is a 16-bit x86 Forth that fits in a 512-byte boot sector.
highway - Performance-portable, length-agnostic SIMD with runtime dispatch
small-lisp - A very small lisp interpreter, that I may one day get working on my 8-bit AVR microcontroller.
highway - Highway - A Modern Javascript Transitions Manager
Carp - A statically typed lisp, without a GC, for real-time applications.
riscv-bitmanip - Working draft of the proposed RISC-V Bitmanipulation extension
mal - mal - Make a Lisp
vroom - VRoom! RISC-V CPU
femtolisp - a lightweight, robust, scheme-like lisp implementation
learn-fpga - Learning FPGA, yosys, nextpnr, and RISC-V
kernel-zig - :floppy_disk: hobby x86 kernel zig