riscv-isa-manual
riscv-pk
riscv-isa-manual | riscv-pk | |
---|---|---|
41 | 7 | |
3,293 | 547 | |
2.6% | 1.1% | |
9.7 | 5.8 | |
4 days ago | 7 days ago | |
TeX | C | |
Creative Commons Attribution 4.0 | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-isa-manual
-
The Improved RISC-V Specification (latest WIP draft)
https://github.com/riscv/riscv-isa-manual/releases
Regarding the recent "How to improve the RISC-V specification" post [0], I just wanted to point out, that the latest draft manual is already a great improvement. (see link above)
It includes a lot of the newly ratified extensions: bitmanip,zicond,vector,vector crypto, ...
And there are a bunch of included SAIL definitions for bitmanip and zicond, but other instructions are still missing the SAIL code. Most notably, the SAIL definitions from the RV32I/RV64I base isa are also missing.
I asked for the further SAIL integration plans here: https://github.com/riscv/riscv-isa-manual/issues/1369
Here is an example SAIL snippet from cpopw:
let bitcount = 0;
-
How to improve the RISC-V specification
I encourage you to look at the newest isa manual draft on github: https://github.com/riscv/riscv-isa-manual/releases
It includes the more recently extensions, and e.g. the bitmanip instructions all have associated pseudo code.
Here is e.g. the code for cpopw:
let bitcount = 0;
- Need help with designing a basic RISC V processor?
-
The legend of “x86 CPUs decode instructions into RISC form internally”
I tried searching the spec [1] for "overflow" and here is what it says at page 17:
> We did not include special instruction-set support for overflow checks on integer arithmetic operations in the base instruction set, as many overflow checks can be cheaply implemented using RISC-V branches.
> For general signed addition, three additional instructions after the addition are required
Is this "cheap", replacing 1 instruction with four? According to some old mainframe era research (cannot find link now), addition is the most often used instruction and they suggest that we should replace each one with four?
Their "rationale" is not rational at all. It doesn't make sense.
Overflow check should be free (no additional instructions required), otherwise we will see the same story we have seen for last 50 years: compiler writers do not want to implement checks because they are expensive; language designers do not want to use proper arithmetic because it is expensive. As a result, there will be errors and vulnerabilities. A vicious circle.
[1] https://github.com/riscv/riscv-isa-manual/releases/download/...
- 64-bit Arm ∩ 64-bit RISC V
- Beginner question: F extension
-
Riscv Ghidra Instruction Manual
Why not use the actual release PDF instead from their github? https://github.com/riscv/riscv-isa-manual
-
How would I go about designing an 8-bit RISC-V CPU? Is it possible?
https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf Part 2
-
Have to convert a C language code into RISC-V MIPS
If you don't want to cheat then read the RISC-V ISA manual: https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf
-
How does a computer understand machine language?
Yeah you are on the right track. Processors are designed on top of an Instruction Set Architecture (ISA). For an example you can look on top of the RISC-V specifications:https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf (possible PDF download)
riscv-pk
- Need help with designing a basic RISC V processor?
- So Im working on making my own OS from scratch. Im using a linux based os for reverse engineering but I need help in understanding how to use the tools that are in rar/zip files. If anyone can direct me to some tutorials or resources to read that would be a big help.
-
How to fix “qemu-system-riscv64: Some ROM regions are overlapping These ROM regions might have been loaded by direct user request or by default.”
The embedded BBL copy in the link you posted is ancient and lacks https://github.com/riscv-software-src/riscv-pk/pull/205
- HELP: riscv-pk
-
How do I learn assembly
I can't recommend the RISC-V Reader, and the proxy kernel, enough. http://riscvbook.com/ https://github.com/riscv-software-src/riscv-pk
-
Amazon gets behind free rival to Arm’s microchips
You can see code in for example pk or bbl (which are built from the same source) to handle this. e.g. https://github.com/riscv/riscv-pk/blob/master/machine/misaligned_ldst.c
-
How to run user program from full system QEMU? (qemu-system-riscv64)
Ok, I see. Unfortunately it seems a bit like it's not supported: https://github.com/riscv/riscv-pk/issues/180 . If you have a GH account, maybe ping the issue for current status?
What are some alternatives?
riscv-elf-psabi-doc - A RISC-V ELF psABI Document
kasirga_gok_2023 - Kasırga - Gök Sayısal İşlemci Kategorisi RISC-V İşlemci Tasarımı
riscv-emulator-docker-image
biriscv - 32-bit Superscalar RISC-V CPU
amaranth - A modern hardware definition language and toolchain based on Python
collapseos - Bootstrap post-collapse technology
riscv-v-spec - Working draft of the proposed RISC-V V vector extension
busybox - Docker Official Image packaging for Busybox
vroom - VRoom! RISC-V CPU
testsuits-for-oskernel
open-source-cs - Video discussing this curriculum:
ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.