riscv-isa-manual
riscv-crypto
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riscv-isa-manual
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The Improved RISC-V Specification (latest WIP draft)
https://github.com/riscv/riscv-isa-manual/releases
Regarding the recent "How to improve the RISC-V specification" post [0], I just wanted to point out, that the latest draft manual is already a great improvement. (see link above)
It includes a lot of the newly ratified extensions: bitmanip,zicond,vector,vector crypto, ...
And there are a bunch of included SAIL definitions for bitmanip and zicond, but other instructions are still missing the SAIL code. Most notably, the SAIL definitions from the RV32I/RV64I base isa are also missing.
I asked for the further SAIL integration plans here: https://github.com/riscv/riscv-isa-manual/issues/1369
Here is an example SAIL snippet from cpopw:
let bitcount = 0;
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How to improve the RISC-V specification
I encourage you to look at the newest isa manual draft on github: https://github.com/riscv/riscv-isa-manual/releases
It includes the more recently extensions, and e.g. the bitmanip instructions all have associated pseudo code.
Here is e.g. the code for cpopw:
let bitcount = 0;
- Need help with designing a basic RISC V processor?
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The legend of “x86 CPUs decode instructions into RISC form internally”
I tried searching the spec [1] for "overflow" and here is what it says at page 17:
> We did not include special instruction-set support for overflow checks on integer arithmetic operations in the base instruction set, as many overflow checks can be cheaply implemented using RISC-V branches.
> For general signed addition, three additional instructions after the addition are required
Is this "cheap", replacing 1 instruction with four? According to some old mainframe era research (cannot find link now), addition is the most often used instruction and they suggest that we should replace each one with four?
Their "rationale" is not rational at all. It doesn't make sense.
Overflow check should be free (no additional instructions required), otherwise we will see the same story we have seen for last 50 years: compiler writers do not want to implement checks because they are expensive; language designers do not want to use proper arithmetic because it is expensive. As a result, there will be errors and vulnerabilities. A vicious circle.
[1] https://github.com/riscv/riscv-isa-manual/releases/download/...
- 64-bit Arm ∩ 64-bit RISC V
- Beginner question: F extension
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Riscv Ghidra Instruction Manual
Why not use the actual release PDF instead from their github? https://github.com/riscv/riscv-isa-manual
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How would I go about designing an 8-bit RISC-V CPU? Is it possible?
https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf Part 2
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Have to convert a C language code into RISC-V MIPS
If you don't want to cheat then read the RISC-V ISA manual: https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf
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How does a computer understand machine language?
Yeah you are on the right track. Processors are designed on top of an Instruction Set Architecture (ISA). For an example you can look on top of the RISC-V specifications:https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf (possible PDF download)
riscv-crypto
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Vector vs SIMD
...and given time, they will likely get the necessary facilities and extensions to compete with packed SIMD in every field (e.g. the cryptography extension makes use of vector element groups in order to operate on 128 bits at a time - which is not possible in a "pure" vector ISA with 32/64-bit vector elements).
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RISC-V announces ratification of it's new Scalar Cryptography & Entropy Source Extensions
Link to the spec: https://github.com/riscv/riscv-crypto/releases
- RISC-V Int. Ratifies 15 New Specs, Opening Up New RISC-V Design Possibilities
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Suggestions for Capstone Projects/Thesis Topics for Post-Graduation Studies in the domain of RISC-V's Security Aspects
What would be the impact of Cryptographic Extension of the RISC-V ISA be, particularly on small IoT devices?
- r/crypto - The RISC-V Scalar Cryptography Extension has reached public review
- The RISC-V Scalar Cryptography Extension has reached public review
- RISC-V Scalar Cryptography Extension reaches public review
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Scalar Cryptography Extensions out for Public Review
Direct link to the latest specification release: https://github.com/riscv/riscv-crypto/releases
What are some alternatives?
riscv-elf-psabi-doc - A RISC-V ELF psABI Document
riscv-v-spec - Working draft of the proposed RISC-V V vector extension
riscv-emulator-docker-image
riscv-bitmanip - Working draft of the proposed RISC-V Bitmanipulation extension
amaranth - A modern hardware definition language and toolchain based on Python
riscv-platform-specs - RISC-V Profiles and Platform Specification
vroom - VRoom! RISC-V CPU
open-source-cs - Video discussing this curriculum:
ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
rocket-chip - Rocket Chip Generator