riscv-isa-manual
collapseos
riscv-isa-manual | collapseos | |
---|---|---|
41 | 96 | |
3,293 | 4,405 | |
2.6% | - | |
9.7 | 0.0 | |
4 days ago | over 2 years ago | |
TeX | C | |
Creative Commons Attribution 4.0 | GNU General Public License v3.0 only |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-isa-manual
-
The Improved RISC-V Specification (latest WIP draft)
https://github.com/riscv/riscv-isa-manual/releases
Regarding the recent "How to improve the RISC-V specification" post [0], I just wanted to point out, that the latest draft manual is already a great improvement. (see link above)
It includes a lot of the newly ratified extensions: bitmanip,zicond,vector,vector crypto, ...
And there are a bunch of included SAIL definitions for bitmanip and zicond, but other instructions are still missing the SAIL code. Most notably, the SAIL definitions from the RV32I/RV64I base isa are also missing.
I asked for the further SAIL integration plans here: https://github.com/riscv/riscv-isa-manual/issues/1369
Here is an example SAIL snippet from cpopw:
let bitcount = 0;
-
How to improve the RISC-V specification
I encourage you to look at the newest isa manual draft on github: https://github.com/riscv/riscv-isa-manual/releases
It includes the more recently extensions, and e.g. the bitmanip instructions all have associated pseudo code.
Here is e.g. the code for cpopw:
let bitcount = 0;
- Need help with designing a basic RISC V processor?
-
The legend of “x86 CPUs decode instructions into RISC form internally”
I tried searching the spec [1] for "overflow" and here is what it says at page 17:
> We did not include special instruction-set support for overflow checks on integer arithmetic operations in the base instruction set, as many overflow checks can be cheaply implemented using RISC-V branches.
> For general signed addition, three additional instructions after the addition are required
Is this "cheap", replacing 1 instruction with four? According to some old mainframe era research (cannot find link now), addition is the most often used instruction and they suggest that we should replace each one with four?
Their "rationale" is not rational at all. It doesn't make sense.
Overflow check should be free (no additional instructions required), otherwise we will see the same story we have seen for last 50 years: compiler writers do not want to implement checks because they are expensive; language designers do not want to use proper arithmetic because it is expensive. As a result, there will be errors and vulnerabilities. A vicious circle.
[1] https://github.com/riscv/riscv-isa-manual/releases/download/...
- 64-bit Arm ∩ 64-bit RISC V
- Beginner question: F extension
-
Riscv Ghidra Instruction Manual
Why not use the actual release PDF instead from their github? https://github.com/riscv/riscv-isa-manual
-
How would I go about designing an 8-bit RISC-V CPU? Is it possible?
https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf Part 2
-
Have to convert a C language code into RISC-V MIPS
If you don't want to cheat then read the RISC-V ISA manual: https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf
-
How does a computer understand machine language?
Yeah you are on the right track. Processors are designed on top of an Instruction Set Architecture (ISA). For an example you can look on top of the RISC-V specifications:https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf (possible PDF download)
collapseos
-
The Enchippening
Something like this is probably a lot more realistic than (as fast) "integrated circuits at home" : http://collapseos.org/
-
Micro Beast: Self contained 8-bit computer kit in a box
http://collapseos.org/
I know the point of it isn't to run on new hardware, but this would be a way to learn it on a stable platform without having to worry about dealing with constant problems from old hardware before trying to implement it on said.
-
Ask HN: We should urge law makers to unlock the bootloaders
There is something called Collapse OS I read about here on HN:
http://collapseos.org/
I myself am a collector of old devices, having raised three kids plus being a web dev. Hate throwing them away too I was just think about this today could I extract the CPUs or RAM or something to reuse rather than destory for the metals. I'd like to learn more hardware but no time.
-
Researchers identify largest ever solar storm in 14,300-year-old tree rings
Some hope for Colapse OS [1] perhaps?
[1] http://collapseos.org
-
Hacking the Timex M851
http://collapseos.org/
Here is a quick guide to the science for those with the brain worms:
- Shining a Light on the Digital Dark Age
- Google abandons work to move Assistant smart speakers to Fuchsia
-
Need help with designing a basic RISC V processor?
Maybe start with sufficient support for a simple OS that allows you to edit and compile programs. Something like FreeDOS or CollapseOs. Once you have that working you can extend it.
-
Subreddit Updates: May 2023
During collapse we'll all be using Dusk OS and post collapse we'll be using cobbled together rugged computers running on Collapse OS. I imagine at that point we can probably put the sub name to a vote. Maybe "r/ordinarylife".
-
A ultra minimalist distro just for fun
Not Linux....but you could just install Kolibri OS for a very light desktop or consider CollapseOS and DuskOS....think Dusk should run bare metal on now and won't be too bloated, but there's always CollapseOS if you prefer to keep things light
What are some alternatives?
riscv-elf-psabi-doc - A RISC-V ELF psABI Document
iiab - Internet-in-a-Box - Build your own LIBRARY OF ALEXANDRIA with a Raspberry Pi !
riscv-emulator-docker-image
lighthouse-of-doom - A simple text-based adventure game
amaranth - A modern hardware definition language and toolchain based on Python
mu - Soul of a tiny new machine. More thorough tests → More comprehensible and rewrite-friendly software → More resilient society.
riscv-v-spec - Working draft of the proposed RISC-V V vector extension
serenity - The Serenity Operating System 🐞
vroom - VRoom! RISC-V CPU
single_file_libs - List of single-file C/C++ libraries.
open-source-cs - Video discussing this curriculum:
Jupiter-II - Another Jupiter Ace computer clone