riscv-fs
F# RISC-V Instruction Set formal specification (by mrLSD)
rtasm
Runtime Assembler for C++ (by kristiandupont)
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-fs
Posts with mentions or reviews of riscv-fs.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-07-28.
rtasm
Posts with mentions or reviews of rtasm.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-07-28.
-
RISC-V CPU formal specification F# edition
I created this for x86 many years ago: https://github.com/kristiandupont/rtasm
It's not an emulator, it allows you to assemble code in C++ at runtime. It breaks down the architecture (as it looked at the time) quite detailed, if you are interested :-)
-
Just-in-time code generation within WebAssembly
I experimented with this for native x86 many years ago (https://github.com/kristiandupont/rtasm). I used it to generate BitBlt functions with no conditionals in the hot paths, which created noticeable performance improvements with no compromise in flexibility. Debugging code like that is painful though!
What are some alternatives?
When comparing riscv-fs and rtasm you can also consider the following projects:
Forvis_RISCV-ISA-Spec - Formal specification of RISC-V Instruction Set
riscv-coq - RISC-V Specification in Coq
RISC-V-Guide - RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.
sail-riscv - Sail RISC-V model
riscv_em - Simple risc-v emulator, able to run linux, written in C.
RVVM - The RISC-V Virtual Machine
arduino-bl808 - Arduino Core for Bouffalo Labs's RISC-V BL808 SOC