riscv-fs
F# RISC-V Instruction Set formal specification (by mrLSD)
Forvis_RISCV-ISA-Spec
Formal specification of RISC-V Instruction Set (by rsnikhil)
| riscv-fs | Forvis_RISCV-ISA-Spec | |
|---|---|---|
| 2 | 1 | |
| 276 | 96 | |
| - | - | |
| 4.1 | 10.0 | |
| 4 months ago | almost 4 years ago | |
| F# | Haskell | |
| MIT License | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-fs
Posts with mentions or reviews of riscv-fs.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-07-28.
Forvis_RISCV-ISA-Spec
Posts with mentions or reviews of Forvis_RISCV-ISA-Spec.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-07-28.
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RISC-V CPU formal specification F# edition
I completely agree. And I specifically draw your attention to the fact that this is not a formal verification, which it would be reasonable to do: Coq, Isabellll, Agda, F* etc. However, Formal Specification. Those. representation of the specification in a formalized form. Haskell example: https://github.com/rsnikhil/Forvis_RISCV-ISA-Spec.
In this case, the term "formal" refers to the formalization of the representation of the specification. And it seems to be already established.
What are some alternatives?
When comparing riscv-fs and Forvis_RISCV-ISA-Spec you can also consider the following projects:
rtasm - Runtime Assembler for C++
riscv-coq - RISC-V Specification in Coq
RISC-V-Guide - RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.
sail-riscv - Sail RISC-V model
riscv_em - Simple risc-v emulator, able to run linux, written in C.
RVVM - The RISC-V Virtual Machine
arduino-bl808 - Arduino Core for Bouffalo Labs's RISC-V BL808 SOC