riscv-isa-manual
RISC-V Instruction Set Manual (by rems-project)
tinyrv
A tiny RISC-V instruction decoder and instruction set simulator (by s-holst)
| riscv-isa-manual | tinyrv | |
|---|---|---|
| 1 | 1 | |
| 1 | 1 | |
| - | - | |
| - | 7.2 | |
| almost 4 years ago | 8 days ago | |
| TeX | Python | |
| Creative Commons Attribution 4.0 | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-isa-manual
Posts with mentions or reviews of riscv-isa-manual.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-04-28.
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How to improve the RISC-V specification
Sail is pretty similar to ASL (both current ASL and ASL 1.0) except that (1) it has a more expressive type system, so that bitvector lengths can all be statically checked, (2) it has proper tagged unions and pattern matching, and (3) there's a wide range of open-source tooling available, for execution, specification coverage, generating emulators, integrating with relaxed concurrency models, generating theorem-prover definitions, etc. We've recently updated the Sail README, which spells some of this out: https://github.com/rems-project/sail .
As Alastair Reid says, one of the main things missing in the current RISC-V specification documents is simply that the associated Sail definitions are not yet interspersed with the prose instruction descriptions. The infrastructure to do that has been available for some time, in the Sail AsciiDoc support by Alasdair Armstrong (https://github.com/Alasdair/asciidoctor-sail/blob/master/doc...) and older LaTeX versions by Prashanth Mundkur and Alasdair (https://github.com/rems-project/riscv-isa-manual/blob/sail/r...).
tinyrv
Posts with mentions or reviews of tinyrv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-04-28.
-
How to improve the RISC-V specification
Here is one in less than 200 lines of python: https://github.com/s-holst/tinyrv .
What are some alternatives?
When comparing riscv-isa-manual and tinyrv you can also consider the following projects:
riscv-opcodes - RISC-V Opcodes