mightyminer
Bitcoin Mining software that drives be the Antminer S1 hashing boards directly via UART (by MightyDevices)
sha256
Hardware implementation of the SHA-256 cryptographic hash function (by secworks)
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mightyminer | sha256 | |
---|---|---|
1 | 4 | |
44 | 300 | |
- | - | |
10.0 | 2.3 | |
about 6 years ago | 11 months ago | |
JavaScript | Verilog | |
MIT License | BSD 2-clause "Simplified" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
mightyminer
Posts with mentions or reviews of mightyminer.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-10-23.
-
Mining software source or ASIC interface specifications
See https://github.com/MightyDevices/mightyminer
sha256
Posts with mentions or reviews of sha256.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-10-23.
-
Reducing Critical Path of Multi-Operand Addition
Hi, I'm trying to improve the performance of the SHA-256 algorithm on an FPGA for an undergraduate research project. My knowledge and experience is quite novel so please correct me if any of my assumptions are wrong. I'm working with this Verilog design: https://github.com/secworks/sha256
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Create an SHA-256 hash function in Verilog
Here is an open source implementation that might be helpful to refer to: https://github.com/secworks/sha256/blob/master/src/rtl/sha256_core.v
- Mining software source or ASIC interface specifications
- Hope Bitcoin hits 1M but I have to unsubscribe. This place is an unhealthy echo chamber of delusion and speculation with little focus on the actual technology.